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Searched refs:__raw_readl (Results 1 – 25 of 498) sorted by relevance

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/linux/arch/mips/sgi-ip22/
A Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
69 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); in eeprom_cmd()
[all …]
/linux/arch/mips/alchemy/common/
A Dusb.c102 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
103 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl()
153 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ohci_control()
168 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ehci_control()
173 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_ehci_control()
190 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_ehci_control()
195 r = __raw_readl(base + USB_DWC_CTRL3); in __au1300_ehci_control()
209 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_udc_control()
226 r = __raw_readl(base + USB_DWC_CTRL1); in __au1300_udc_control()
395 unsigned long r = __raw_readl(base); in au1000_usb_init()
[all …]
/linux/arch/mips/loongson32/common/
A Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
86 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
92 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/linux/arch/arm/mach-s3c/
A Dpm-gpio.c36 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume()
37 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume()
123 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_2bit_resume()
124 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_2bit_resume()
244 u32 old_gpcon = __raw_readl(con); in samsung_gpio_pm_4bit_con()
260 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_4bit_resume()
266 old_gpcon[1] = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_4bit_resume()
270 old_gpcon[0] = __raw_readl(base - 4); in samsung_gpio_pm_4bit_resume()
287 __raw_readl(base - 4), in samsung_gpio_pm_4bit_resume()
288 __raw_readl(base + OFFS_CON), in samsung_gpio_pm_4bit_resume()
[all …]
A Dpm-core-s3c24xx.h20 unsigned long tmp = __raw_readl(S3C2410_CLKCON); in s3c_pm_debug_init_uart()
39 __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND); in s3c_pm_arch_prepare_irqs()
40 __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND); in s3c_pm_arch_prepare_irqs()
41 __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND); in s3c_pm_arch_prepare_irqs()
71 __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
72 __raw_readl(S3C2410_EINTPEND)); in s3c_pm_arch_show_resume_irqs()
74 s3c_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND), in s3c_pm_arch_show_resume_irqs()
77 s3c_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND), in s3c_pm_arch_show_resume_irqs()
A Dgpio-samsung.c47 pup = __raw_readl(reg); in samsung_gpio_setpull_updown()
60 u32 pup = __raw_readl(reg); in samsung_gpio_getpull_updown()
113 u32 pup = __raw_readl(reg); in s3c24xx_gpio_setpull_1()
131 u32 pup = __raw_readl(reg); in s3c24xx_gpio_getpull_1()
190 con = __raw_readl(reg); in samsung_gpio_setcfg_2bit()
213 con = __raw_readl(chip->base); in samsung_gpio_getcfg_2bit()
253 con = __raw_readl(reg); in samsung_gpio_setcfg_4bit()
283 con = __raw_readl(reg); in samsung_gpio_getcfg_4bit()
321 con = __raw_readl(reg); in s3c24xx_gpio_setcfg_abank()
572 con = __raw_readl(regcon); in samsung_gpiolib_4bit2_input()
[all …]
/linux/arch/mips/pci/
A Dops-tx4927.c82 if (__raw_readl(&pcicptr->pcistatus) in check_abort()
110 return __raw_readl(&pcicptr->g2pcfgdata); in icd_readl()
230 __raw_readl(&pcicptr->pciid) >> 16, in tx4927_pcic_setup()
231 __raw_readl(&pcicptr->pciid) & 0xffff, in tx4927_pcic_setup()
232 __raw_readl(&pcicptr->pciccrev) & 0xff, in tx4927_pcic_setup()
239 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
307 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
312 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
316 __raw_writel(__raw_readl(&pcicptr->pciccfg) in tx4927_pcic_setup()
361 __raw_readl(&pcicptr->g2ptocnt) & 0xff, in tx4927_pcic_setup()
[all …]
A Dpci-ar724x.c86 data = __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
108 __raw_readl(base + (where & ~3)); in ar724x_pci_local_write()
128 data = __raw_readl(base + (where & ~3)); in ar724x_pci_read()
197 data = __raw_readl(base + (where & ~3)); in ar724x_pci_write()
219 __raw_readl(base + (where & ~3)); in ar724x_pci_write()
239 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_handler()
261 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
265 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_unmask()
282 t = __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_mask()
287 __raw_readl(base + AR724X_PCI_REG_INT_MASK); in ar724x_pci_irq_mask()
[all …]
A Dpci-alchemy.c114 r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; in config_access()
157 *data = __raw_readl(ctx->pci_cfg_vm->addr + offset); in config_access()
164 status = __raw_readl(ctx->regs + PCI_REG_STATCMD); in config_access()
313 ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); in alchemy_pci_suspend()
320 ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); in alchemy_pci_suspend()
321 ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); in alchemy_pci_suspend()
322 ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); in alchemy_pci_suspend()
323 ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); in alchemy_pci_suspend()
324 ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); in alchemy_pci_suspend()
434 val = __raw_readl(ctx->regs + PCI_REG_CONFIG); in alchemy_pci_probe()
[all …]
A Dpci-ar71xx.c113 pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; in ar71xx_pci_check_error()
118 addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); in ar71xx_pci_check_error()
127 ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; in ar71xx_pci_check_error()
132 addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); in ar71xx_pci_check_error()
193 data = __raw_readl(base + AR71XX_PCI_REG_CFG_RDDATA); in ar71xx_pci_read_config()
234 pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) & in ar71xx_pci_irq_handler()
235 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_handler()
263 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
267 __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_unmask()
280 t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE); in ar71xx_pci_irq_mask()
[all …]
/linux/arch/arm/mach-pxa/
A Dsmemc.c22 msc[0] = __raw_readl(MSC0); in pxa3xx_smemc_suspend()
23 msc[1] = __raw_readl(MSC1); in pxa3xx_smemc_suspend()
24 sxcnfg = __raw_readl(SXCNFG); in pxa3xx_smemc_suspend()
25 memclkcfg = __raw_readl(MEMCLKCFG); in pxa3xx_smemc_suspend()
26 csadrcfg[0] = __raw_readl(CSADRCFG0); in pxa3xx_smemc_suspend()
27 csadrcfg[1] = __raw_readl(CSADRCFG1); in pxa3xx_smemc_suspend()
28 csadrcfg[2] = __raw_readl(CSADRCFG2); in pxa3xx_smemc_suspend()
29 csadrcfg[3] = __raw_readl(CSADRCFG3); in pxa3xx_smemc_suspend()
/linux/arch/arm/mach-mmp/
A Dpm-mmp2.c47 data |= __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake()
52 data = ~data & __raw_readl(MPMU_WUCRM_PJ); in mmp2_set_wake()
68 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_disable()
84 val = __raw_readl(CIU_REG(0x1c)); in pm_scu_clk_enable()
105 val = __raw_readl(MPMU_PLL2_CTRL1); in pm_mpmu_clk_enable()
116 idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG); in mmp2_pm_enter_lowpower_mode()
117 apcr = __raw_readl(MPMU_PCR_PJ); in mmp2_pm_enter_lowpower_mode()
162 temp = __raw_readl(MMP2_ICU_INT4_MASK); in mmp2_pm_enter()
168 temp = __raw_readl(APMU_SRAM_PWR_DWN); in mmp2_pm_enter()
237 __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8)); in mmp2_pm_init()
[all …]
A Dpm-pxa910.c112 awucrm |= __raw_readl(MPMU_AWUCRM); in pxa910_set_wake()
116 apcr = ~apcr & __raw_readl(MPMU_APCR); in pxa910_set_wake()
121 awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM); in pxa910_set_wake()
125 apcr |= __raw_readl(MPMU_APCR); in pxa910_set_wake()
136 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter_lowpower_mode()
137 apcr = __raw_readl(MPMU_APCR); in pxa910_pm_enter_lowpower_mode()
192 reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT)); in pxa910_pm_enter()
196 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
215 idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
262 __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30), in pxa910_pm_init()
[all …]
/linux/arch/sh/boards/mach-dreamcast/
A Drtc.c39 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
40 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
42 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_gettimeofday()
43 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_gettimeofday()
71 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
72 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
74 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) | in aica_rtc_settimeofday()
75 (__raw_readl(AICA_RTC_SECS_L) & 0xffff); in aica_rtc_settimeofday()
/linux/arch/mips/ath79/
A Dclock.c105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
253 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG); in ar934x_clocks_init()
257 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG); in ar934x_clocks_init()
265 pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); in ar934x_clocks_init()
280 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG); in ar934x_clocks_init()
284 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG); in ar934x_clocks_init()
292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
368 pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG); in qca953x_clocks_init()
382 pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG); in qca953x_clocks_init()
[all …]
/linux/drivers/soc/ixp4xx/
A Dixp4xx-qmgr.c43 val = __raw_readl(&qmgr_regs->acc[queue][0]); in qmgr_get_entry()
55 return (__raw_readl(&qmgr_regs->stat1[queue >> 3]) in __qmgr_get_stat1()
62 return (__raw_readl(&qmgr_regs->stat2[queue >> 4]) in __qmgr_get_stat2()
87 return (__raw_readl(&qmgr_regs->statne_h) >> in qmgr_stat_below_low_watermark()
101 return (__raw_readl(&qmgr_regs->statf_h) >> in qmgr_stat_full()
149 en_bitmap = __raw_readl(&qmgr_regs->irqen[0]); in qmgr_irq1_a0()
153 src = __raw_readl(&qmgr_regs->irqsrc[i >> 3]); in qmgr_irq1_a0()
154 stat = __raw_readl(&qmgr_regs->stat1[i >> 3]); in qmgr_irq1_a0()
175 __raw_readl(&qmgr_regs->statne_h); in qmgr_irq2_a0()
287 if (__raw_readl(&qmgr_regs->sram[queue])) { in qmgr_request_queue()
[all …]
/linux/drivers/edac/
A Dcpc925_edac.c394 mccr = __raw_readl(pdata->vbase + REG_MCCR_OFFSET); in cpc925_mc_init()
533 mesr = __raw_readl(pdata->vbase + REG_MESR_OFFSET); in cpc925_mc_check()
536 mear = __raw_readl(pdata->vbase + REG_MEAR_OFFSET); in cpc925_mc_check()
560 __raw_readl(pdata->vbase + REG_APIMASK_OFFSET)); in cpc925_mc_check()
564 __raw_readl(pdata->vbase + REG_MSCR_OFFSET)); in cpc925_mc_check()
566 __raw_readl(pdata->vbase + REG_MSRSR_OFFSET)); in cpc925_mc_check()
568 __raw_readl(pdata->vbase + REG_MSRER_OFFSET)); in cpc925_mc_check()
570 __raw_readl(pdata->vbase + REG_MSPR_OFFSET)); in cpc925_mc_check()
572 __raw_readl(pdata->vbase + REG_MCCR_OFFSET)); in cpc925_mc_check()
574 __raw_readl(pdata->vbase + REG_MCRER_OFFSET)); in cpc925_mc_check()
[all …]
/linux/drivers/soc/samsung/
A Ds3c-pm-debug.c51 save->ulcon = __raw_readl(regs + S3C2410_ULCON); in s3c_pm_save_uarts()
52 save->ucon = __raw_readl(regs + S3C2410_UCON); in s3c_pm_save_uarts()
53 save->ufcon = __raw_readl(regs + S3C2410_UFCON); in s3c_pm_save_uarts()
54 save->umcon = __raw_readl(regs + S3C2410_UMCON); in s3c_pm_save_uarts()
55 save->ubrdiv = __raw_readl(regs + S3C2410_UBRDIV); in s3c_pm_save_uarts()
58 save->udivslot = __raw_readl(regs + S3C2443_DIVSLOT); in s3c_pm_save_uarts()
/linux/arch/arm/mach-cns3xxx/
A Dpm.c17 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_en()
26 u32 reg = __raw_readl(PM_CLK_GATE_REG); in cns3xxx_pwr_clk_dis()
35 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_up()
47 u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); in cns3xxx_pwr_power_down()
57 u32 reg = __raw_readl(PM_SOFT_RST_REG); in cns3xxx_pwr_soft_rst_force()
105 u32 reg = __raw_readl(PM_CLK_CTRL_REG); in cns3xxx_cpu_clock()
/linux/drivers/irqchip/
A Dirq-ath79-misc.c41 pending = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS) & in ath79_misc_irq_handler()
42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ath79_misc_irq_handler()
66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_unmask()
79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()
83 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); in ar71xx_misc_irq_mask()
92 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); in ar724x_misc_irq_ack()
96 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS); in ar724x_misc_irq_ack()
/linux/drivers/char/hw_random/
A Dmxc-rnga.c68 int level = (__raw_readl(mxc_rng->mem + RNGA_STATUS) & in mxc_rnga_data_present()
84 *data = __raw_readl(mxc_rng->mem + RNGA_OUTPUT_FIFO); in mxc_rnga_data_read()
87 err = __raw_readl(mxc_rng->mem + RNGA_STATUS) & RNGA_STATUS_ERROR_INT; in mxc_rnga_data_read()
92 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_data_read()
106 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_init()
110 osc = __raw_readl(mxc_rng->mem + RNGA_STATUS); in mxc_rnga_init()
117 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_init()
128 ctrl = __raw_readl(mxc_rng->mem + RNGA_CONTROL); in mxc_rnga_cleanup()
/linux/arch/arm/mach-davinci/
A Dpm.c51 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
58 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
64 val = __raw_readl(pm_config.deepsleep_reg); in davinci_pm_suspend()
75 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
80 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
88 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
96 val = __raw_readl(pm_config.cpupll_reg_base + PLLCTL); in davinci_pm_suspend()
/linux/arch/sh/kernel/cpu/sh4a/
A Dubc.c50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
69 if (__raw_readl(UBC_CBR(i)) & UBC_CBR_CE) in sh4a_ubc_active_mask()
77 return __raw_readl(UBC_CCMFR); in sh4a_ubc_triggered_mask()
82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
121 (void)__raw_readl(UBC_CRR(i)); in sh4a_ubc_init()
A Dsmp-shx3.c34 x = __raw_readl(0xfe410070 + offs); /* C0INITICI..CnINTICI */ in ipi_interrupt_handler()
51 __raw_writel(__raw_readl(STBCR_REG(cpu)) | STBCR_LTSLP, STBCR_REG(cpu)); in shx3_smp_setup()
91 if (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu()
94 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_start_cpu()
103 return __raw_readl(0xff000048); /* CPIDR */ in shx3_smp_processor_id()
118 while (!(__raw_readl(STBCR_REG(cpu)) & STBCR_MSTP)) in shx3_update_boot_vector()
/linux/sound/soc/au1x/
A Dpsc-ac97.c92 if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) in au1xpsc_ac97_read()
96 data = __raw_readl(AC97_CDC(pscdata)); in au1xpsc_ac97_read()
132 if (__raw_readl(AC97_EVNT(pscdata)) & PSC_AC97EVNT_CD) in au1xpsc_ac97_write()
179 while (!((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_SR)) && (--i)) in au1xpsc_ac97_cold_reset()
217 r = ro = __raw_readl(AC97_CFG(pscdata)); in au1xpsc_ac97_hw_params()
218 stat = __raw_readl(AC97_STAT(pscdata)); in au1xpsc_ac97_hw_params()
256 while ((__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR) && --t) in au1xpsc_ac97_hw_params()
272 while ((!(__raw_readl(AC97_STAT(pscdata)) & PSC_AC97STAT_DR)) && --t) in au1xpsc_ac97_hw_params()
309 while (__raw_readl(AC97_STAT(pscdata)) & AC97STAT_BUSY(stype)) in au1xpsc_ac97_trigger()
395 sel = __raw_readl(PSC_SEL(wd)) & PSC_SEL_CLK_MASK; in au1xpsc_ac97_drvprobe()
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