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Searched refs:__raw_readw (Results 1 – 25 of 159) sorted by relevance

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/linux/arch/sh/boards/mach-sh7763rdp/
A Dsetup.c163 if (__raw_readw(CPLD_BOARD_ID_ERV_REG) == 0xECB1) in sh7763rdp_setup()
169 __raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2); in sh7763rdp_setup()
171 __raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR); in sh7763rdp_setup()
178 __raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR); in sh7763rdp_setup()
180 __raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR); in sh7763rdp_setup()
184 __raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2); in sh7763rdp_setup()
186 __raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3); in sh7763rdp_setup()
190 __raw_writew((__raw_readw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1); in sh7763rdp_setup()
192 __raw_writew(__raw_readw(PORT_PSEL4) | 0x4000, PORT_PSEL4); in sh7763rdp_setup()
205 __raw_writew(__raw_readw(PORT_PACR) & ~0x3000, PORT_PACR); in sh7763rdp_setup()
[all …]
/linux/arch/sh/boards/mach-se/7206/
A Dirq.c37 val = __raw_readw(INTC_IPR01); in disable_se7206_irq()
41 msk0 = __raw_readw(INTMSK0); in disable_se7206_irq()
42 msk1 = __raw_readw(INTMSK1); in disable_se7206_irq()
68 val = __raw_readw(INTC_IPR01); in enable_se7206_irq()
73 msk0 = __raw_readw(INTMSK0); in enable_se7206_irq()
74 msk1 = __raw_readw(INTMSK1); in enable_se7206_irq()
100 sts0 = __raw_readw(INTSTS0); in eoi_se7206_irq()
101 sts1 = __raw_readw(INTSTS1); in eoi_se7206_irq()
143 __raw_writew(__raw_readw(INTC_ICR1) | 0x000b, INTC_ICR1); /* ICR1 */ in init_se7206_IRQ()
/linux/arch/sh/include/mach-se/mach/
A Dmrshpc.h9 if ((__raw_readw(MRSHPC_CSR) & 0x000c) != 0) in mrshpc_setup_windows()
12 if ((__raw_readw(MRSHPC_CSR) & 0x0080) == 0) { in mrshpc_setup_windows()
24 if((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
33 if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
43 if ((__raw_readw(MRSHPC_CSR) & 0x4000) != 0) in mrshpc_setup_windows()
/linux/arch/sh/boot/romimage/
A Dmmcif-sh7724.c48 __raw_writew(__raw_readw(PTXCR) & ~0x000f, PTXCR); in mmcif_loader()
51 __raw_writew(__raw_readw(PSELA) & ~0x2000, PSELA); in mmcif_loader()
54 __raw_writew(__raw_readw(PSELE) & ~0x3000, PSELE); in mmcif_loader()
57 __raw_writew(__raw_readw(HIZCRC) & ~0x0620, HIZCRC); in mmcif_loader()
60 __raw_writew(__raw_readw(DRVCRA) | 0x3000, DRVCRA); in mmcif_loader()
/linux/arch/sh/kernel/cpu/sh3/
A Dserial-sh7720.c16 data = __raw_readw(PORT_PTCR); in sh7720_sci_init_pins()
20 data = __raw_readw(PORT_PVCR); in sh7720_sci_init_pins()
26 data = __raw_readw(PORT_PTCR); in sh7720_sci_init_pins()
30 data = __raw_readw(PORT_PVCR); in sh7720_sci_init_pins()
A Dclock-sh7710.c26 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
35 int idx = (__raw_readw(FRQCR) & 0x0007); in module_clk_recalc()
45 int idx = (__raw_readw(FRQCR) & 0x0700) >> 8; in bus_clk_recalc()
55 int idx = (__raw_readw(FRQCR) & 0x0070) >> 4; in cpu_clk_recalc()
A Dclock-sh7705.c32 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; in master_clk_init()
41 int idx = __raw_readw(FRQCR) & 0x0003; in module_clk_recalc()
51 int idx = (__raw_readw(FRQCR) & 0x0300) >> 8; in bus_clk_recalc()
61 int idx = (__raw_readw(FRQCR) & 0x0030) >> 4; in cpu_clk_recalc()
A Dclock-sh3.c28 int frqcr = __raw_readw(FRQCR); in master_clk_init()
40 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
52 int frqcr = __raw_readw(FRQCR); in bus_clk_recalc()
64 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
A Dclock-sh7706.c24 int frqcr = __raw_readw(FRQCR); in master_clk_init()
36 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
48 int frqcr = __raw_readw(FRQCR); in bus_clk_recalc()
60 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
A Dclock-sh7709.c24 int frqcr = __raw_readw(FRQCR); in master_clk_init()
36 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
48 int frqcr = __raw_readw(FRQCR); in bus_clk_recalc()
61 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
A Dserial-sh7710.c13 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR); in sh7710_sci_init_pins()
14 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR); in sh7710_sci_init_pins()
16 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR); in sh7710_sci_init_pins()
A Dclock-sh7712.c23 int frqcr = __raw_readw(FRQCR); in master_clk_init()
35 int frqcr = __raw_readw(FRQCR); in module_clk_recalc()
47 int frqcr = __raw_readw(FRQCR); in cpu_clk_recalc()
/linux/arch/sh/kernel/cpu/sh4/
A Dclock-sh4.c28 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007]; in master_clk_init()
37 int idx = (__raw_readw(FRQCR) & 0x0007); in module_clk_recalc()
47 int idx = (__raw_readw(FRQCR) >> 3) & 0x0007; in bus_clk_recalc()
57 int idx = (__raw_readw(FRQCR) >> 6) & 0x0007; in cpu_clk_recalc()
/linux/arch/sh/kernel/cpu/sh2a/
A Dclock-sh7201.c27 pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in master_clk_init()
36 int idx = (__raw_readw(FREQCR) & 0x0007); in module_clk_recalc()
46 int idx = (__raw_readw(FREQCR) & 0x0007); in bus_clk_recalc()
56 int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007); in cpu_clk_recalc()
A Dclock-sh7206.c26 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in master_clk_init()
35 int idx = (__raw_readw(FREQCR) & 0x0007); in module_clk_recalc()
45 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007]; in bus_clk_recalc()
54 int idx = (__raw_readw(FREQCR) & 0x0007); in cpu_clk_recalc()
A Dclock-sh7203.c29 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * pll2_mult; in master_clk_init()
38 int idx = (__raw_readw(FREQCR) & 0x0007); in module_clk_recalc()
48 int idx = (__raw_readw(FREQCR) & 0x0007); in bus_clk_recalc()
/linux/arch/sparc/include/asm/
A Dide.h44 *ps++ = __raw_readw(port); in __ide_insw()
51 w = __raw_readw(port) << 16; in __ide_insw()
52 w |= __raw_readw(port); in __ide_insw()
58 *ps++ = __raw_readw(port); in __ide_insw()
/linux/arch/nds32/include/asm/
A Dio.h36 #define __raw_readw __raw_readw macro
37 static inline u16 __raw_readw(const volatile void __iomem *addr) in __raw_readw() function
64 #define readw_relaxed(c) ({ u16 __v = le16_to_cpu((__force __le16)__raw_readw(c)); __v; })
/linux/arch/m68k/include/asm/
A Dio_no.h18 #define __raw_readw(addr) \ macro
69 return __raw_readw(addr); in readw()
70 return swab16(__raw_readw(addr)); in readw()
102 #define readw __raw_readw
/linux/arch/sh/kernel/cpu/sh2/
A Dclock-sh7619.c25 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in master_clk_init()
34 int idx = (__raw_readw(FREQCR) & 0x0007); in module_clk_recalc()
44 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7]; in bus_clk_recalc()
/linux/arch/h8300/include/asm/
A Dio.h17 #define __raw_readw __raw_readw macro
18 static inline u16 __raw_readw(const volatile void __iomem *addr) in __raw_readw() function
/linux/include/asm-generic/
A Dlogic_io.h42 #define __raw_readw __raw_readw macro
43 u16 __raw_readw(const volatile void __iomem *addr);
/linux/arch/arm64/include/asm/
A Dio.h59 #define __raw_readw __raw_readw macro
60 static inline u16 __raw_readw(const volatile void __iomem *addr) in __raw_readw() function
121 #define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; })
177 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(__v); __…
/linux/arch/arc/include/asm/
A Dio.h40 #define ioread16be(p) ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
63 #define __raw_readw __raw_readw macro
64 static inline u16 __raw_readw(const volatile void __iomem *addr) in __raw_readw() function
225 __raw_readw(c)); __r; })
/linux/arch/arm/include/asm/
A Dio.h59 #define __raw_readw(a) (__chk_io_ptr(a), *(volatile unsigned short __force *)(a)) macro
74 #define __raw_readw __raw_readw macro
75 static inline u16 __raw_readw(const volatile void __iomem *addr) in __raw_readw() function
261 __raw_readw(__io(p))); __iormb(); __v; })
294 __raw_readw(c)); __r; })
408 #define ioread16be(p) ({ __u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; …

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