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Searched refs:__raw_writel (Results 1 – 25 of 503) sorted by relevance

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/linux/arch/mips/alchemy/common/
A Dirq.c293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask()
523 __raw_writel(l, r + AU1300_GPIC_PINCFG); in au1300_gpic_chgcfg()
608 __raw_writel(bit, r + AU1300_GPIC_IDIS); in au1300_gpic_mask()
625 __raw_writel(bit, r + AU1300_GPIC_IEN); in au1300_gpic_unmask()
749 __raw_writel(d[0], base + IC_CFG0SET); in alchemy_ic_resume_one()
750 __raw_writel(d[1], base + IC_CFG1SET); in alchemy_ic_resume_one()
751 __raw_writel(d[2], base + IC_CFG2SET); in alchemy_ic_resume_one()
752 __raw_writel(d[3], base + IC_SRCSET); in alchemy_ic_resume_one()
753 __raw_writel(d[4], base + IC_ASSIGNSET); in alchemy_ic_resume_one()
754 __raw_writel(d[5], base + IC_WAKESET); in alchemy_ic_resume_one()
[all …]
A Dusb.c112 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
118 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl()
134 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
145 __raw_writel(0, base + USB_DWC_CTRL7); in __au1300_ohci_control()
156 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control()
170 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ehci_control()
175 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
192 __raw_writel(r, base + USB_DWC_CTRL1); in __au1300_ehci_control()
417 __raw_writel(r, base); in au1000_usb_init()
519 __raw_writel(0, base + 0x04); in au1000_usb_pm()
[all …]
A Dvss.c34 __raw_writel(0x01, base + VSS_FTR); in __enable_block()
36 __raw_writel(0x03, base + VSS_FTR); in __enable_block()
38 __raw_writel(0x07, base + VSS_FTR); in __enable_block()
40 __raw_writel(0x0f, base + VSS_FTR); in __enable_block()
43 __raw_writel(0x01ffffff, base + VSS_GATE); /* start FSM too */ in __enable_block()
46 __raw_writel(2, base + VSS_CLKRST); /* deassert reset */ in __enable_block()
49 __raw_writel(0x1f, base + VSS_FTR); /* enable isolation cells */ in __enable_block()
60 __raw_writel(0, base + VSS_GATE); /* disable FSM */ in __disable_block()
62 __raw_writel(3, base + VSS_CLKRST); /* assert reset */ in __disable_block()
64 __raw_writel(1, base + VSS_CLKRST); /* disable clock */ in __disable_block()
[all …]
/linux/arch/mips/kernel/
A Dcevt-txx9.c63 __raw_writel(TCR_BASE, &tmrptr->tcr); in txx9_clocksource_init()
64 __raw_writel(0, &tmrptr->tisr); in txx9_clocksource_init()
85 __raw_writel(0, &tmrptr->tisr); in txx9tmr_stop_and_clear()
122 __raw_writel(0, &tmrptr->itmr); in txx9tmr_set_state_shutdown()
134 __raw_writel(0, &tmrptr->itmr); in txx9tmr_tick_resume()
147 __raw_writel(delta, &tmrptr->cpra); in txx9tmr_set_next_event()
186 __raw_writel(0, &tmrptr->itmr); in txx9_clockevent_init()
214 __raw_writel(0, &tmrptr->tisr); in txx9_tmr_init()
216 __raw_writel(0, &tmrptr->itmr); in txx9_tmr_init()
217 __raw_writel(0, &tmrptr->ccdr); in txx9_tmr_init()
[all …]
A Dirq_txx9.c72 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_unmask()
77 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_unmask()
78 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_unmask()
88 __raw_writel((__raw_readl(ilrp) & ~(0xff << ofs)) in txx9_irq_mask()
93 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_mask()
94 __raw_writel(irc_elevel, &txx9_ircptr->imr); in txx9_irq_mask()
135 __raw_writel(cr, crp); in txx9_irq_set_type()
162 __raw_writel(0, &txx9_ircptr->imr); in txx9_irq_init()
164 __raw_writel(0, &txx9_ircptr->ilr[i]); in txx9_irq_init()
167 __raw_writel(0, &txx9_ircptr->cr[i]); in txx9_irq_init()
[all …]
/linux/arch/arm/mach-mmp/
A Dtime.c52 __raw_writel(1, mmp_timer_base + TMR_CVWR(1)); in timer_read()
72 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_interrupt()
77 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_interrupt()
94 __raw_writel(0x02, mmp_timer_base + TMR_CER); in timer_set_next_event()
99 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0)); in timer_set_next_event()
100 __raw_writel(0x01, mmp_timer_base + TMR_IER(0)); in timer_set_next_event()
110 __raw_writel(0x03, mmp_timer_base + TMR_CER); in timer_set_next_event()
160 __raw_writel(ccr, mmp_timer_base + TMR_CCR); in timer_config()
163 __raw_writel(0x2, mmp_timer_base + TMR_CMR); in timer_config()
167 __raw_writel(0x0, mmp_timer_base + TMR_IER(0)); in timer_config()
[all …]
A Dpm-mmp2.c48 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
53 __raw_writel(data, MPMU_WUCRM_PJ); in mmp2_set_wake()
64 __raw_writel(0x0, CIU_REG(0x64)); in pm_scu_clk_disable()
65 __raw_writel(0x0, CIU_REG(0x68)); in pm_scu_clk_disable()
70 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_disable()
86 __raw_writel(val, CIU_REG(0x1c)); in pm_scu_clk_enable()
97 __raw_writel(0x0000a010, MPMU_CGR_PJ); in pm_mpmu_clk_disable()
104 __raw_writel(0xdffefffe, MPMU_CGR_PJ); in pm_mpmu_clk_enable()
107 __raw_writel(val, MPMU_PLL2_CTRL1); in pm_mpmu_clk_enable()
230 __raw_writel(0x5, MPMU_SCCR); in mmp2_pm_init()
[all …]
A Dpm-pxa910.c113 __raw_writel(awucrm, MPMU_AWUCRM); in pxa910_set_wake()
117 __raw_writel(apcr, MPMU_APCR); in pxa910_set_wake()
122 __raw_writel(awucrm, MPMU_AWUCRM); in pxa910_set_wake()
126 __raw_writel(apcr, MPMU_APCR); in pxa910_set_wake()
172 __raw_writel(0x0, APMU_MC_HW_SLP_TYPE); /* auto refresh */ in pxa910_pm_enter_lowpower_mode()
182 __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); in pxa910_pm_enter_lowpower_mode()
183 __raw_writel(apcr, MPMU_APCR); in pxa910_pm_enter_lowpower_mode()
199 __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
218 __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); in pxa910_pm_enter()
264 __raw_writel(__raw_readl(MPMU_FCCR) | (1 << 28), MPMU_FCCR); in pxa910_pm_init()
[all …]
/linux/arch/mips/sgi-ip22/
A Dip22-nvram.c36 __raw_writel(__raw_readl(ptr) & ~EEPROM_DATO, ptr); \
37 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
38 __raw_writel(__raw_readl(ptr) & ~EEPROM_EPROT, ptr); \
40 __raw_writel(__raw_readl(ptr) | EEPROM_CSEL, ptr); \
41 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
45 __raw_writel(__raw_readl(ptr) & ~EEPROM_ECLK, ptr); \
46 __raw_writel(__raw_readl(ptr) & ~EEPROM_CSEL, ptr); \
47 __raw_writel(__raw_readl(ptr) | EEPROM_EPROT, ptr); \
48 __raw_writel(__raw_readl(ptr) | EEPROM_ECLK, ptr); })
69 __raw_writel(__raw_readl(ctrl) | EEPROM_ECLK, ctrl); in eeprom_cmd()
[all …]
/linux/arch/mips/pci/
A Dops-tx4927.c64 __raw_writel(((bus->number & 0xff) << 0x10) in mkaddr()
130 __raw_writel(val, &pcicptr->g2pcfgdata); in icd_writel()
261 __raw_writel(0, &pcicptr->g2pmmask[i]); in tx4927_pcic_setup()
266 __raw_writel((channel->mem_resource->end in tx4927_pcic_setup()
284 __raw_writel(0, &pcicptr->p2gm0plbase); in tx4927_pcic_setup()
285 __raw_writel(0, &pcicptr->p2gm0pubase); in tx4927_pcic_setup()
302 __raw_writel((tx4927_pci_opts.gbwc << 16) in tx4927_pcic_setup()
321 __raw_writel(0, &pcicptr->pcicfg1); in tx4927_pcic_setup()
346 __raw_writel(0, &pcicptr->pbabm); in tx4927_pcic_setup()
510 __raw_writel(0, &pcicptr->pbabm); in tx4927_quirk_slc90e66_bridge()
[all …]
/linux/arch/sh/drivers/pci/
A Dpci-sh7780.c127 __raw_writel(cmd, hose->reg_base + SH4_PCIAINT); in sh7780_pci_err_irq()
140 __raw_writel(cmd, hose->reg_base + SH4_PCIINT); in sh7780_pci_err_irq()
169 __raw_writel(0, hose->reg_base + SH4_PCIAINT); in sh7780_pci_setup_irqs()
231 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
241 __raw_writel(tmp, hose->reg_base + SH4_PCICR); in sh7780_pci66_init()
258 __raw_writel(PCIECR_ENBL, PCIECR); in sh7780_pci_init()
296 __raw_writel(SH4_PCICR_PREFIX | PCICR_ENDIANNESS, in sh7780_pci_init()
315 __raw_writel(0, chan->reg_base + SH4_PCILAR1); in sh7780_pci_init()
316 __raw_writel(0, chan->reg_base + SH4_PCILSR1); in sh7780_pci_init()
324 __raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1, in sh7780_pci_init()
[all …]
/linux/sound/soc/au1x/
A Dpsc-ac97.c78 __raw_writel(PSC_AC97EVNT_CD, AC97_EVNT(pscdata)); in au1xpsc_ac97_read()
148 __raw_writel(PSC_AC97RST_SNC, AC97_RST(pscdata)); in au1xpsc_ac97_warm_reset()
151 __raw_writel(0, AC97_RST(pscdata)); in au1xpsc_ac97_warm_reset()
170 __raw_writel(0, AC97_RST(pscdata)); in au1xpsc_ac97_cold_reset()
263 __raw_writel(r, AC97_CFG(pscdata)); in au1xpsc_ac97_hw_params()
396 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); in au1xpsc_ac97_drvprobe()
398 __raw_writel(0, PSC_SEL(wd)); in au1xpsc_ac97_drvprobe()
430 __raw_writel(0, AC97_CFG(wd)); in au1xpsc_ac97_drvremove()
432 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); in au1xpsc_ac97_drvremove()
448 __raw_writel(0, AC97_CFG(wd)); in au1xpsc_ac97_drvsuspend()
[all …]
A Dpsc-i2s.c159 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
173 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_configure()
228 __raw_writel(0, I2S_CFG(pscdata)); in au1xpsc_i2s_stop()
321 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); in au1xpsc_i2s_drvprobe()
324 __raw_writel(0, I2S_CFG(wd)); in au1xpsc_i2s_drvprobe()
350 __raw_writel(0, I2S_CFG(wd)); in au1xpsc_i2s_drvremove()
352 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); in au1xpsc_i2s_drvremove()
366 __raw_writel(0, I2S_CFG(wd)); in au1xpsc_i2s_drvsuspend()
368 __raw_writel(PSC_CTRL_DISABLE, PSC_CTRL(wd)); in au1xpsc_i2s_drvsuspend()
381 __raw_writel(0, PSC_SEL(wd)); in au1xpsc_i2s_drvresume()
[all …]
/linux/arch/mips/loongson32/common/
A Dirq.c28 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_ack()
37 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask()
46 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_mask_ack()
48 __raw_writel(__raw_readl(LS1X_INTC_INTCLR(n)) in ls1x_irq_mask_ack()
57 __raw_writel(__raw_readl(LS1X_INTC_INTIEN(n)) in ls1x_irq_unmask()
68 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
74 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
80 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
86 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
92 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n)) in ls1x_irq_settype()
[all …]
/linux/arch/arm/mach-s3c/
A Dmach-n30.c455 __raw_writel(0x00000000, S3C2410_GPADAT); in n30_hwinit()
470 __raw_writel(0x00154556, S3C2410_GPBCON); in n30_hwinit()
471 __raw_writel(0x00000750, S3C2410_GPBDAT); in n30_hwinit()
472 __raw_writel(0x00000073, S3C2410_GPBUP); in n30_hwinit()
489 __raw_writel(0xaaa80618, S3C2410_GPCCON); in n30_hwinit()
491 __raw_writel(0x0000fef2, S3C2410_GPCUP); in n30_hwinit()
503 __raw_writel(0x0000fbfe, S3C2410_GPDUP); in n30_hwinit()
512 __raw_writel(0x0000f81f, S3C2410_GPEUP); in n30_hwinit()
527 __raw_writel(0x000000ff, S3C2410_GPFUP); in n30_hwinit()
557 __raw_writel(0x0000f86f, S3C2410_GPGUP); in n30_hwinit()
[all …]
A Dpm-s3c2416.c27 __raw_writel(S3C2443_PWRCFG_SLEEP, S3C2443_PWRCFG); in s3c2416_cpu_suspend()
30 __raw_writel(0x2BED, S3C2443_PWRMODE); in s3c2416_cpu_suspend()
45 __raw_writel(0x2BED, S3C2412_INFORM0); in s3c2416_pm_prepare()
46 __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1); in s3c2416_pm_prepare()
74 __raw_writel(0x0, S3C2443_PWRMODE); in s3c2416_pm_resume()
75 __raw_writel(0x0, S3C2412_INFORM0); in s3c2416_pm_resume()
76 __raw_writel(0x0, S3C2412_INFORM1); in s3c2416_pm_resume()
/linux/arch/m68k/coldfire/
A Dpci.c71 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_readconfig()
87 __raw_writel(0, PCICAR); in mcf_pci_readconfig()
103 __raw_writel(PCICAR_E | addr, PCICAR); in mcf_pci_writeconfig()
115 __raw_writel(cpu_to_le32(value), addr); in mcf_pci_writeconfig()
119 __raw_writel(0, PCICAR); in mcf_pci_writeconfig()
178 __raw_writel(PCIGSCR_RESET, PCIGSCR); in mcf_pci_init()
179 __raw_writel(0, PCITCR); in mcf_pci_init()
195 __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1); in mcf_pci_init()
196 __raw_writel(0, PCICR2); in mcf_pci_init()
214 __raw_writel(CONFIG_RAMBASE, PCIBAR1); in mcf_pci_init()
[all …]
/linux/arch/arm/mach-pxa/
A Dsmemc.c36 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
37 __raw_writel(msc[1], MSC1); in pxa3xx_smemc_resume()
38 __raw_writel(sxcnfg, SXCNFG); in pxa3xx_smemc_resume()
39 __raw_writel(memclkcfg, MEMCLKCFG); in pxa3xx_smemc_resume()
40 __raw_writel(csadrcfg[0], CSADRCFG0); in pxa3xx_smemc_resume()
41 __raw_writel(csadrcfg[1], CSADRCFG1); in pxa3xx_smemc_resume()
42 __raw_writel(csadrcfg[2], CSADRCFG2); in pxa3xx_smemc_resume()
43 __raw_writel(csadrcfg[3], CSADRCFG3); in pxa3xx_smemc_resume()
45 __raw_writel(0x2, CSMSADRCFG); in pxa3xx_smemc_resume()
64 __raw_writel(0x2, CSMSADRCFG); in smemc_init()
/linux/arch/sh/mm/
A Dtlb-pteaex.c32 __raw_writel(vpn, MMU_PTEH); in __update_tlb()
35 __raw_writel(get_asid(), MMU_PTEAEX); in __update_tlb()
47 __raw_writel(pte.pte_high, MMU_PTEA); in __update_tlb()
56 __raw_writel(pteval, MMU_PTEL); in __update_tlb()
73 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
74 __raw_writel(asid, MMU_UTLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
75 __raw_writel(page, MMU_ITLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
76 __raw_writel(asid, MMU_ITLB_ADDRESS_ARRAY2 | MMU_PAGE_ASSOC_BIT); in local_flush_tlb_one()
98 __raw_writel(0x0, MMU_UTLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
101 __raw_writel(0x0, MMU_ITLB_ADDRESS_ARRAY | (i << 8)); in local_flush_tlb_all()
/linux/arch/sh/kernel/cpu/sh4a/
A Dubc.c34 __raw_writel(UBC_CBR_CE | info->len | info->type, UBC_CBR(idx)); in sh4a_ubc_enable()
35 __raw_writel(info->address, UBC_CAR(idx)); in sh4a_ubc_enable()
40 __raw_writel(0, UBC_CBR(idx)); in sh4a_ubc_disable()
41 __raw_writel(0, UBC_CAR(idx)); in sh4a_ubc_disable()
50 __raw_writel(__raw_readl(UBC_CBR(i)) | UBC_CBR_CE, in sh4a_ubc_enable_all()
59 __raw_writel(__raw_readl(UBC_CBR(i)) & ~UBC_CBR_CE, in sh4a_ubc_disable_all()
82 __raw_writel(__raw_readl(UBC_CCMFR) & ~mask, UBC_CCMFR); in sh4a_ubc_clear_triggered_mask()
112 __raw_writel(0, UBC_CBCR); in sh4a_ubc_init()
115 __raw_writel(0, UBC_CAMR(i)); in sh4a_ubc_init()
116 __raw_writel(0, UBC_CBR(i)); in sh4a_ubc_init()
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
A Dau1000_dma.h160 __raw_writel(DMA_BE0, chan->io + DMA_MODE_SET); in enable_dma_buffer0()
169 __raw_writel(DMA_BE1, chan->io + DMA_MODE_SET); in enable_dma_buffer1()
186 __raw_writel(DMA_GO, chan->io + DMA_MODE_SET); in start_dma()
198 __raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR); in halt_dma()
218 __raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR); in disable_dma()
248 __raw_writel(~mode, chan->io + DMA_MODE_CLEAR); in init_dma()
249 __raw_writel(mode, chan->io + DMA_MODE_SET); in init_dma()
319 __raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR); in clear_dma_done0()
328 __raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR); in clear_dma_done1()
347 __raw_writel(a, chan->io + DMA_BUFFER0_START); in set_dma_addr0()
[all …]
/linux/arch/mips/txx9/generic/
A Dirq_tx4939.c66 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) in tx4939_irq_unmask()
84 __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs)) in tx4939_irq_mask()
141 __raw_writel(cr, crp); in tx4939_irq_set_type()
172 __raw_writel(0, &tx4939_ircptr->den.r); in tx4939_irq_init()
173 __raw_writel(0, &tx4939_ircptr->maskint.r); in tx4939_irq_init()
174 __raw_writel(0, &tx4939_ircptr->maskext.r); in tx4939_irq_init()
184 __raw_writel(0, &tx4939_ircptr->msk.r); in tx4939_irq_init()
186 __raw_writel(0, &tx4939_ircptr->lvl[i].r); in tx4939_irq_init()
189 __raw_writel(0, &tx4939_ircptr->dm[i].r); in tx4939_irq_init()
191 __raw_writel(0, &tx4939_ircptr->dm2[i].r); in tx4939_irq_init()
[all …]
/linux/arch/arm/mach-lpc32xx/
A Dserial.c109 __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg); in lpc32xx_serial_init()
116 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
117 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
122 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
126 __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE); in lpc32xx_serial_init()
130 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
131 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart)); in lpc32xx_serial_init()
135 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart)); in lpc32xx_serial_init()
141 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
146 __raw_writel(tmp, LPC32XX_UARTCTL_CTRL); in lpc32xx_serial_init()
/linux/arch/mips/ath79/
A Dcommon.c61 __raw_writel(0x1, flush_reg); in ath79_ddr_wb_flush()
66 __raw_writel(0x1, flush_reg); in ath79_ddr_wb_flush()
76 __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0); in ath79_ddr_set_pci_windows()
77 __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4); in ath79_ddr_set_pci_windows()
78 __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8); in ath79_ddr_set_pci_windows()
79 __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc); in ath79_ddr_set_pci_windows()
80 __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10); in ath79_ddr_set_pci_windows()
81 __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14); in ath79_ddr_set_pci_windows()
82 __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18); in ath79_ddr_set_pci_windows()
83 __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c); in ath79_ddr_set_pci_windows()
/linux/drivers/clocksource/
A Dtimer-vf-pit.c38 __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); in pit_timer_enable()
43 __raw_writel(0, clkevt_base + PITTCTRL); in pit_timer_disable()
48 __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); in pit_irq_acknowledge()
59 __raw_writel(0, clksrc_base + PITTCTRL); in pit_clocksource_init()
60 __raw_writel(~0UL, clksrc_base + PITLDVAL); in pit_clocksource_init()
61 __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); in pit_clocksource_init()
79 __raw_writel(delta - 1, clkevt_base + PITLDVAL); in pit_set_next_event()
128 __raw_writel(0, clkevt_base + PITTCTRL); in pit_clockevent_init()
129 __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); in pit_clockevent_init()
186 __raw_writel(~PITMCR_MDIS, timer_base + PITMCR); in pit_timer_init()

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