Searched refs:_clk (Results 1 – 9 of 9) sorted by relevance
| /linux/include/linux/ |
| A D | sh_clk.h | 200 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } argument
201 #define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } argument
202 #define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk } argument
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| /linux/arch/arm/mach-omap2/ |
| A D | omap_hwmod.c | 833 oh->_clk = clk; in _init_main_clk()
888 os->_clk = c; in _init_interface_clks()
925 oc->_clk = c; in _init_opt_clks()
948 if (oc->_clk) { in _enable_optional_clocks()
963 if (oc->_clk) { in _disable_optional_clocks()
986 if (oh->_clk) in _enable_clocks()
1041 if (oh->_clk) in _disable_clocks()
2407 if (!os->_clk) in _setup_iclk_autoidle()
3789 if (oh->_clk) { in omap_hwmod_get_pwrdm()
3790 c = oh->_clk; in omap_hwmod_get_pwrdm()
[all …]
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| A D | omap_hwmod.h | 181 struct clk *_clk; member
244 struct clk *_clk; member
585 struct clk *_clk; member
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| A D | display.c | 388 clk_prepare_enable(oc->_clk); in omap_dss_reset()
414 clk_disable_unprepare(oc->_clk); in omap_dss_reset()
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| /linux/drivers/scsi/ufs/ |
| A D | ufs-exynos.c | 502 unsigned long clk = 0, _clk, clk_period; in exynos_ufs_calc_pwm_clk_div() local
507 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); in exynos_ufs_calc_pwm_clk_div()
508 if (_clk >= pwm_min && _clk <= pwm_max) { in exynos_ufs_calc_pwm_clk_div()
509 if (_clk > clk) { in exynos_ufs_calc_pwm_clk_div()
511 clk = _clk; in exynos_ufs_calc_pwm_clk_div()
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| /linux/Documentation/devicetree/bindings/media/ |
| A D | cdns,csi2rx.txt | 14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
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| A D | cdns,csi2tx.txt | 15 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| A D | gm20b.c | 852 struct gm20b_clk *_clk = gm20b_clk(base); in gm20b_clk_init() local
856 _clk->uv = nvkm_volt_get(volt); in gm20b_clk_init()
859 ret = gm20b_clk_init_dvfs(_clk); in gm20b_clk_init()
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| /linux/drivers/clk/renesas/ |
| A D | r9a06g032-clocks.c | 60 #define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \ argument
61 { .gate = _clk, .reset = _rst, \
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