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/linux/drivers/clk/sprd/
A Dgate.h42 .hw.init = _fn(_name, _parent, \
50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \
75 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \
85 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
97 #define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
100 SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \
104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
[all …]
A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
80 .hw.init = _fn(_name, _parent, \
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument
108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \
[all …]
A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
30 .hw.init = _fn(_name, _parent, \
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \
53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
55 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
A Ddiv.h38 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
45 .hw.init = _fn(_name, _parent, \
50 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument
52 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
55 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument
57 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
/linux/drivers/clk/mediatek/
A Dclk-mt8195-infra_ao.c44 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao0_cg_regs, _shift, \
47 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
48 GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, 0)
51 GATE_MTK_FLAGS(_id, _name, _parent, &infra_ao1_cg_regs, _shift, \
54 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
55 GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, 0)
57 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
64 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
65 GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, 0)
71 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
45 GATE_MTK(_id, _name, _parent, &ipu_conn_cg_regs, _shift, \
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
49 GATE_MTK(_id, _name, _parent, &ipu_conn_apb_cg_regs, _shift, \
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
53 GATE_MTK(_id, _name, _parent, &ipu_conn_axi_cg_regs, _shift, \
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
57 GATE_MTK(_id, _name, _parent, &ipu_conn_axi1_cg_regs, _shift, \
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
61 GATE_MTK(_id, _name, _parent, &ipu_conn_axi2_cg_regs, _shift, \
A Dclk-mt8192.c923 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
930 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
931 GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, 0)
933 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
940 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
941 GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, 0)
943 #define GATE_INFRA4(_id, _name, _parent, _shift) \ argument
950 #define GATE_INFRA5(_id, _name, _parent, _shift) \ argument
951 GATE_INFRA5_FLAGS(_id, _name, _parent, _shift, 0)
1095 #define GATE_PERI(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt8195-vdo1.c37 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vdo1_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
40 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
41 GATE_MTK(_id, _name, _parent, &vdo1_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
43 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
44 GATE_MTK(_id, _name, _parent, &vdo1_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
46 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
47 GATE_MTK(_id, _name, _parent, &vdo1_3_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
A Dclk-mt8192-vdec.c33 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
34 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
36 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
37 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
39 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
40 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
A Dclk-mt8167.c660 .parent_name = _parent, \
690 .parent_name = _parent, \
738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
741 .parent_name = _parent, \
750 .parent_name = _parent, \
759 .parent_name = _parent, \
768 .parent_name = _parent, \
777 .parent_name = _parent, \
786 .parent_name = _parent, \
795 .parent_name = _parent, \
[all …]
A Dclk-mt8195-vdec.c31 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &vdec0_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
34 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &vdec1_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
37 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vdec2_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
A Dclk-mt2701-aud.c18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
21 .parent_name = _parent, \
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
30 .parent_name = _parent, \
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
39 .parent_name = _parent, \
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
48 .parent_name = _parent, \
A Dclk-mt7622-aud.c19 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
22 .parent_name = _parent, \
28 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
31 .parent_name = _parent, \
37 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
40 .parent_name = _parent, \
46 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
49 .parent_name = _parent, \
A Dclk-mt8192-mm.c32 #define GATE_MM0(_id, _name, _parent, _shift) \ argument
33 GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
35 #define GATE_MM1(_id, _name, _parent, _shift) \ argument
36 GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
38 #define GATE_MM2(_id, _name, _parent, _shift) \ argument
39 GATE_MTK(_id, _name, _parent, &mm2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
A Dclk-mt8195-vpp0.c31 #define GATE_VPP0_0(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VPP0_1(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VPP0_2(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
A Dclk-mt8192-aud.c33 #define GATE_AUD0(_id, _name, _parent, _shift) \ argument
34 GATE_MTK(_id, _name, _parent, &aud0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
36 #define GATE_AUD1(_id, _name, _parent, _shift) \ argument
37 GATE_MTK(_id, _name, _parent, &aud1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
39 #define GATE_AUD2(_id, _name, _parent, _shift) \ argument
40 GATE_MTK(_id, _name, _parent, &aud2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
A Dclk-mt8195-vdo0.c31 #define GATE_VDO0_0(_id, _name, _parent, _shift) \ argument
32 GATE_MTK(_id, _name, _parent, &vdo0_0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
34 #define GATE_VDO0_1(_id, _name, _parent, _shift) \ argument
35 GATE_MTK(_id, _name, _parent, &vdo0_1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
37 #define GATE_VDO0_2(_id, _name, _parent, _shift) \ argument
38 GATE_MTK(_id, _name, _parent, &vdo0_2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
/linux/drivers/clk/renesas/
A Drzg2l-cpg.h87 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
88 DEF_TYPE(_name, _id, _type, .parent = _parent)
89 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
93 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ argument
95 #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ argument
97 .parent = _parent, .dtable = _dtable, .flag = _flag)
130 .parent = (_parent), \
136 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ argument
137 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, false)
139 #define DEF_COUPLED(_name, _id, _parent, _off, _bit) \ argument
[all …]
A Drenesas-cpg-mssr.h46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
47 DEF_TYPE(_name, _id, _type, .parent = _parent)
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
52 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
54 DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
76 { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
83 #define DEF_MOD_STB(_name, _mod, _parent...) \ argument
[all …]
A Drcar-gen3-cpg.h35 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
36 DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
48 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
49 DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
55 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
56 DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
/linux/sound/soc/mediatek/mt8195/
A Dmt8195-audsys-clk.c31 .parent_name = _parent, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
[all …]
/linux/drivers/clk/actions/
A Dowl-composite.h37 #define OWL_COMP_DIV(_struct, _name, _parent, \ argument
46 _parent, \
52 #define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ argument
60 _parent, \
66 #define OWL_COMP_FACTOR(_struct, _name, _parent, \ argument
75 _parent, \
81 #define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \ argument
91 _parent, \
97 #define OWL_COMP_PASS(_struct, _name, _parent, \ argument
105 _parent, \
/linux/drivers/clk/sunxi-ng/
A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
25 _parent, \
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
37 _parent, \
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
49 _parent, \
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
65 _parent, \
A Dccu_nm.h38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
55 _parent, \
61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
79 _parent, \
85 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \ argument
105 _parent, \
112 _parent, _reg, \ argument
134 _parent, \
140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument
152 _parent, \
A Dccu_div.h87 #define SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ argument
97 _parent, \
104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument
107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \
149 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument
158 _parent, \
164 #define SUNXI_CCU_M(_struct, _name, _parent, _reg, _mshift, _mwidth, \ argument
166 SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \

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123456