/linux/drivers/net/ethernet/amd/xgbe/ |
A D | xgbe-common.h | 1467 _reg##_##_field##_INDEX, \ 1468 _reg##_##_field##_WIDTH) 1477 _reg##_##_field##_INDEX, \ 1492 _reg##_##_field##_INDEX, \ 1493 _reg##_##_field##_WIDTH) 1518 _reg##_##_field##_WIDTH) 1576 _reg##_##_field##_WIDTH) 1596 _reg##_##_field##_WIDTH) 1619 _reg##_##_field##_WIDTH) 1652 _reg##_##_field##_WIDTH) [all …]
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/linux/drivers/clk/sprd/ |
A D | gate.h | 41 .reg = _reg, \ 50 SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ 56 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ 66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument 68 SPRD_SC_GATE_CLK_OPS(_struct, _name, _parent, _reg, 0, \ 75 SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ 100 SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \ 104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument 119 _reg, _sc_offset, \ argument 131 _reg, _sc_offset, \ [all …]
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A D | pll.h | 64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument 79 .reg = _reg, \ 85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument 88 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \ 92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument 95 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ 99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument 101 SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ 105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument 108 SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, _regs_num, \ [all …]
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A D | composite.h | 21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument 29 .reg = _reg, \ 35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument 37 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ 41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument 43 SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, NULL, \ 46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument 49 SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ 53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument 55 SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, NULL, \
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A D | mux.h | 40 _reg, _shift, _width, _flags, _fn) \ argument 45 .reg = _reg, \ 52 _reg, _shift, _width, _flags) \ argument 54 _reg, _shift, _width, _flags, \ 57 #define SPRD_MUX_CLK(_struct, _name, _parents, _reg, \ argument 60 _reg, _shift, _width, _flags) 63 _reg, _shift, _width, _flags) \ argument 65 _reg, _shift, _width, _flags, \ 68 #define SPRD_MUX_CLK_DATA(_struct, _name, _parents, _reg, \ argument 71 _reg, _shift, _width, _flags)
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A D | div.h | 38 #define SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument 44 .reg = _reg, \ 50 #define SPRD_DIV_CLK(_struct, _name, _parent, _reg, \ argument 52 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ 55 #define SPRD_DIV_CLK_HW(_struct, _name, _parent, _reg, \ argument 57 SPRD_DIV_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \
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/linux/drivers/regulator/ |
A D | mc13xxx.h | 66 .reg = prefix ## _reg, \ 67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ 73 #define MC13xxx_FIXED_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument 84 .reg = prefix ## _reg, \ 85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ 88 #define MC13xxx_GPO_DEFINE(prefix, _name, _node, _reg, _voltages, _ops) \ argument 99 .reg = prefix ## _reg, \ 100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \ 103 #define MC13xxx_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages, ops) \ argument 104 MC13xxx_DEFINE(SW, _name, _node, _reg, _vsel_reg, _voltages, ops) [all …]
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/linux/drivers/clk/sunxi-ng/ |
A D | ccu_div.h | 95 .reg = _reg, \ 104 #define SUNXI_CCU_DIV_TABLE(_struct, _name, _parent, _reg, \ argument 107 SUNXI_CCU_DIV_TABLE_WITH_GATE(_struct, _name, _parent, _reg, \ 113 _reg, \ argument 122 .reg = _reg, \ 135 _reg, _mshift, _mwidth, \ 139 #define SUNXI_CCU_M_WITH_MUX(_struct, _name, _parents, _reg, \ argument 144 _reg, _mshift, _mwidth, \ 149 #define SUNXI_CCU_M_WITH_GATE(_struct, _name, _parent, _reg, \ argument 156 .reg = _reg, \ [all …]
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A D | ccu_gate.h | 19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument 23 .reg = _reg, \ 31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument 35 .reg = _reg, \ 43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument 47 .reg = _reg, \ 59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument 63 .reg = _reg, \ 71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument 75 .reg = _reg, \
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A D | ccu_mp.h | 34 #define SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(_struct, _name, _parents, _reg, \ argument 46 .reg = _reg, \ 55 #define SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument 66 .reg = _reg, \ 74 #define SUNXI_CCU_MP_WITH_MUX(_struct, _name, _parents, _reg, \ argument 79 SUNXI_CCU_MP_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ 103 #define SUNXI_CCU_MP_MMC_WITH_MUX_GATE(_struct, _name, _parents, _reg, \ argument 111 .reg = _reg, \
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A D | ccu_nm.h | 38 #define SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(_struct, _name, _parent, _reg, \ argument 52 .reg = _reg, \ 61 #define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(_struct, _name, _parent, _reg, \ argument 76 .reg = _reg, \ 86 _reg, _min_rate, \ argument 102 .reg = _reg, \ 112 _parent, _reg, \ argument 131 .reg = _reg, \ 140 #define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \ argument 150 .reg = _reg, \
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A D | ccu_mux.h | 50 _reg, _shift, _width, _gate, \ argument 56 .reg = _reg, \ 64 #define SUNXI_CCU_MUX_WITH_GATE(_struct, _name, _parents, _reg, \ argument 67 _reg, _shift, _width, _gate, \ 70 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument 73 _reg, _shift, _width, 0, _flags)
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/linux/drivers/clk/pistachio/ |
A D | clk.h | 19 #define GATE(_id, _name, _pname, _reg, _shift) \ argument 22 .reg = _reg, \ 39 #define MUX(_id, _name, _pnames, _reg, _shift) \ argument 42 .reg = _reg, \ 59 #define DIV(_id, _name, _pname, _reg, _width) \ argument 62 .reg = _reg, \ 72 .reg = _reg, \ 119 #define PLL(_id, _name, _pname, _type, _reg, _rates) \ argument 122 .reg_base = _reg, \ 130 #define PLL_FIXED(_id, _name, _pname, _type, _reg) \ argument [all …]
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/linux/drivers/clk/mediatek/ |
A D | clk-mtk.h | 82 #define MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, _shift, \ argument 86 .mux_reg = _reg, \ 89 .gate_reg = _reg, \ 102 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument 104 MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ 112 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ 115 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument 116 MUX_FLAGS(_id, _name, _parents, _reg, \ 122 .mux_reg = _reg, \ 191 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument [all …]
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/linux/arch/mips/include/asm/mach-pic32/ |
A D | pic32.h | 14 #define PIC32_CLR(_reg) ((_reg) + 0x04) argument 15 #define PIC32_SET(_reg) ((_reg) + 0x08) argument 16 #define PIC32_INV(_reg) ((_reg) + 0x0C) argument
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/linux/drivers/clk/x86/ |
A D | clk-cgu.h | 123 _reg, _type) \ argument 130 .reg = _reg, \ 162 .reg = _reg, \ 206 #define LGM_MUX(_id, _name, _pdata, _f, _reg, \ argument 215 .mux_off = _reg, \ 234 .div_off = _reg, \ 244 #define LGM_GATE(_id, _name, _pname, _f, _reg, \ argument 256 .gate_off = _reg, \ 262 #define LGM_FIXED(_id, _name, _pname, _f, _reg, \ argument 274 .div_off = _reg, \ [all …]
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/linux/arch/mips/include/asm/ |
A D | kvm_host.h | 440 return cop0->reg[(_reg)][(sel)]; \ 445 cop0->reg[(_reg)][(sel)] = val; \ 453 cop0->reg[(_reg)][(sel)] |= val; \ 458 cop0->reg[(_reg)][(sel)] &= ~val; \ 465 cop0->reg[(_reg)][(sel)] &= ~_mask; \ 466 cop0->reg[(_reg)][(sel)] |= val & _mask; \ 526 #define __BUILD_KVM_SAVE_VZ(name, _reg, sel) \ argument 529 write_gc0_##name(cop0->reg[(_reg)][(sel)]); \ 607 __BUILD_KVM_RW_VZ(name, type, _reg, sel) \ 609 __BUILD_KVM_SAVE_VZ(name, _reg, sel) [all …]
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/linux/drivers/clk/actions/ |
A D | owl-pll.h | 41 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ argument 44 .reg = _reg, \ 55 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx, \ argument 58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ 70 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx, \ argument 73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \ 84 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \ argument 88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
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A D | owl-gate.h | 27 #define OWL_GATE_HW(_reg, _bit_idx, _gate_flags) \ argument 29 .reg = _reg, \ 34 #define OWL_GATE(_struct, _name, _parent, _reg, \ argument 37 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \ 47 #define OWL_GATE_NO_PARENT(_struct, _name, _reg, \ argument 50 .gate_hw = OWL_GATE_HW(_reg, _bit_idx, _gate_flags), \
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/linux/drivers/clk/meson/ |
A D | axg-audio.c | 25 .offset = (_reg), \ 39 .offset = (_reg), \ 55 .offset = (_reg), \ 71 .offset = (_reg), \ 86 .reg_off = (_reg), \ 91 .reg_off = (_reg), \ 109 .reg_off = (_reg), \ 114 .reg_off = (_reg), \ 119 .reg_off = (_reg), \ 136 .reg_off = (_reg), \ [all …]
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A D | clk-regmap.h | 117 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument 120 .offset = (_reg), \ 132 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument 133 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) 135 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument 136 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
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/linux/drivers/media/tuners/ |
A D | mc44s803_priv.h | 179 #define MC44S803_REG_SM(_val, _reg) \ argument 180 (((_val) << _reg##_S) & (_reg)) 183 #define MC44S803_REG_MS(_val, _reg) \ argument 184 (((_val) & (_reg)) >> _reg##_S)
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/linux/drivers/gpu/drm/i915/gvt/ |
A D | reg.h | 80 #define REG_50080_TO_PIPE(_reg) ({ \ argument 81 typeof(_reg) (reg) = (_reg); \ 87 #define REG_50080_TO_PLANE(_reg) ({ \ argument 88 typeof(_reg) (reg) = (_reg); \
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/linux/include/linux/ |
A D | sh_clk.h | 151 #define SH_CLK_DIV4(_parent, _reg, _shift, _div_bitmap, _flags) \ argument 154 .enable_reg = (void __iomem *)_reg, \ 175 #define SH_CLK_DIV6_EXT(_reg, _flags, _parents, \ argument 178 .enable_reg = (void __iomem *)_reg, \ 188 #define SH_CLK_DIV6(_parent, _reg, _flags) \ argument 191 .enable_reg = (void __iomem *)_reg, \ 205 #define SH_CLK_FSIDIV(_reg, _parent) \ argument 207 .enable_reg = (void __iomem *)_reg, \
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/linux/drivers/net/wireless/ath/ath5k/ |
A D | ath5k.h | 126 (((_val) << _flags##_S) & (_flags)), _reg) 130 (_mask)) | (_flags), _reg) 133 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 136 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 139 #define AR5K_REG_READ_Q(ah, _reg, _queue) \ argument 140 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 142 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ argument 143 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 145 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ argument 146 _reg |= 1 << _queue; \ [all …]
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