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/linux/drivers/clk/sunxi-ng/
A Dccu_div.h46 .width = _width, \
57 .width = _width, \
67 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, 0, _flags)
69 #define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \ argument
70 _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, 0)
75 #define _SUNXI_CCU_DIV(_shift, _width) \ argument
76 _SUNXI_CCU_DIV_FLAGS(_shift, _width, 0)
88 _shift, _width, \ argument
91 .div = _SUNXI_CCU_DIV_TABLE(_shift, _width, \
105 _shift, _width, \ argument
[all …]
A Dccu_mux.h32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument
35 .width = _width, \
39 #define _SUNXI_CCU_MUX(_shift, _width) \ argument
40 _SUNXI_CCU_MUX_TABLE(_shift, _width, NULL)
50 _reg, _shift, _width, _gate, \ argument
54 .mux = _SUNXI_CCU_MUX_TABLE(_shift, _width, _table), \
65 _shift, _width, _gate, _flags) \ argument
67 _reg, _shift, _width, _gate, \
70 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
73 _reg, _shift, _width, 0, _flags)
A Dccu_mult.h17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument
23 .width = _width, \
26 #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ argument
27 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, _min, 0)
29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument
30 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, 1, 0)
32 #define _SUNXI_CCU_MULT(_shift, _width) \ argument
33 _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, 1, 1, 0)
A Dccu_phase.h20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
23 .width = _width, \
/linux/drivers/clk/sprd/
A Dmux.h32 #define _SPRD_MUX_CLK(_shift, _width, _table) \ argument
35 .width = _width, \
40 _reg, _shift, _width, _flags, _fn) \ argument
52 _reg, _shift, _width, _flags) \ argument
54 _reg, _shift, _width, _flags, \
58 _shift, _width, _flags) \ argument
60 _reg, _shift, _width, _flags)
63 _reg, _shift, _width, _flags) \ argument
65 _reg, _shift, _width, _flags, \
69 _shift, _width, _flags) \ argument
[all …]
A Ddiv.h27 #define _SPRD_DIV_CLK(_shift, _width) \ argument
30 .width = _width, \
39 _shift, _width, _flags, _fn) \ argument
41 .div = _SPRD_DIV_CLK(_shift, _width), \
51 _shift, _width, _flags) \ argument
53 _shift, _width, _flags, CLK_HW_INIT)
56 _shift, _width, _flags) \ argument
58 _shift, _width, _flags, CLK_HW_INIT_HW)
/linux/drivers/clk/mediatek/
A Dclk-mtk.h83 _width, _gate, _flags, _muxflags) { \ argument
88 .mux_width = _width, \
102 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument
105 _shift, _width, _gate, _flags, 0)
111 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument
112 MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
115 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument
117 _shift, _width, CLK_SET_RATE_PARENT)
124 .mux_width = _width, \
191 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
[all …]
A Dclk-mux.h41 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
50 .mux_width = _width, \
63 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
66 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
71 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
75 _width, _gate, _upd_ofs, _upd, \
79 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
82 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \
A Dclk-mt8167.c657 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
663 .div_width = _width, \
687 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
693 .div_width = _width, \
/linux/drivers/clk/actions/
A Dowl-pll.h42 _width, _min_mul, _max_mul, _delay, _table) \ argument
48 .width = _width, \
56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
59 _width, _min_mul, _max_mul, \
71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument
74 _width, _min_mul, _max_mul, \
85 _shift, _width, _min_mul, _max_mul, _delay, _table, \ argument
89 _width, _min_mul, _max_mul, \
A Dowl-mux.h27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument
31 .width = _width, \
35 _shift, _width, _flags) \ argument
37 .mux_hw = OWL_MUX_HW(_reg, _shift, _width), \
A Dowl-divider.h29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument
33 .width = _width, \
39 _shift, _width, _table, _div_flags, _flags) \ argument
41 .div_hw = OWL_DIVIDER_HW(_reg, _shift, _width, \
A Dowl-factor.h35 #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \ argument
39 .width = _width, \
45 _shift, _width, _table, _fct_flags, _flags) \ argument
48 _width, _fct_flags, _table), \
/linux/drivers/clk/x86/
A Dclk-cgu.h207 _shift, _width, _cf, _v) \ argument
217 .mux_width = _width, \
222 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \ argument
236 .div_width = _width, \
263 _shift, _width, _cf, _freq, _v) \ argument
276 .div_width = _width, \
283 _shift, _width, _cf, _v, _m, _d) \ argument
296 .div_width = _width, \
/linux/drivers/clk/pistachio/
A Dclk.h59 #define DIV(_id, _name, _pname, _reg, _width) \ argument
63 .width = _width, \
69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
73 .width = _width, \
/linux/drivers/clk/bcm/
A Dclk-kona.h299 #define DIVIDER(_offset, _shift, _width) \ argument
303 .u.s.width = (_width), \
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
313 .u.s.width = (_width), \
350 #define SELECTOR(_offset, _shift, _width) \ argument
354 .width = (_width), \
/linux/drivers/dma/fsl-dpaa2-qdma/
A Ddpdmai.h45 #define MAKE_UMASK64(_width) \ argument
46 ((u64)((_width) < 64 ? ((u64)1 << (_width)) - 1 : (u64)-1))
A Ddpdmai.c36 #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
37 ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg))
/linux/drivers/pinctrl/berlin/
A Dberlin.h37 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
41 .bit_width = _width, \
/linux/drivers/net/ethernet/amd/xgbe/
A Dxgbe-common.h1408 #define GET_BITS(_var, _index, _width) \ argument
1409 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1411 #define SET_BITS(_var, _index, _width, _val) \ argument
1413 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1414 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1417 #define GET_BITS_LE(_var, _index, _width) \ argument
1418 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1420 #define SET_BITS_LE(_var, _index, _width, _val) \ argument
1422 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
1424 ((0x1 << (_width)) - 1)) << (_index))); \
/linux/drivers/clk/
A Dclk-stm32mp1.c1192 .width = _width,\
1200 DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\
1213 .width = _width,\
1320 .width = _width,\
1328 #define _MUX(_offset, _shift, _width, _mux_flags)\ argument
1329 _STM32_MUX(_offset, _shift, _width, _mux_flags, NULL, NULL)\
1671 .width = _width,\
1679 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\ argument
1680 _K_MUX(_id, _offset, _shift, _width, _mux_flags,\
1683 #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\ argument
[all …]
/linux/drivers/clk/meson/
A Dclk-phase.c13 #define phase_step(_width) (360 / (1 << (_width))) argument
A Daxg-audio.c53 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ argument
57 .width = (_width), \
105 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ argument
111 .width = (_width), \
116 .width = (_width), \
121 .width = (_width), \
133 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ argument
138 .width = (_width), \
150 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ argument
156 .width = (_width), \
[all …]
/linux/include/uapi/linux/
A Dv4l2-dv-timings.h25 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ argument
26 { .bt = { _width , ## args } }
28 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ argument
29 .bt = { _width , ## args }
/linux/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_netdev.c16 #define ifh_encode_bitfield(ifh, value, pos, _width) \ argument
18 u32 width = (_width); \

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