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Searched refs:asic_type (Results 1 – 25 of 102) sorted by relevance

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/linux/drivers/misc/habanalabs/common/
A Dhabanalabs_drv.c75 enum hl_asic_type asic_type; in get_asic_type() local
79 asic_type = ASIC_GOYA; in get_asic_type()
82 asic_type = ASIC_GAUDI; in get_asic_type()
85 asic_type = ASIC_GAUDI_SEC; in get_asic_type()
88 asic_type = ASIC_INVALID; in get_asic_type()
92 return asic_type; in get_asic_type()
97 switch (asic_type) { in is_asic_secured()
295 enum hl_asic_type asic_type, int minor) in create_hdev() argument
311 if (hdev->asic_type == ASIC_INVALID) { in create_hdev()
317 hdev->asic_type = asic_type; in create_hdev()
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A Dsysfs.c251 switch (hdev->asic_type) { in device_type_show()
263 hdev->asic_type); in device_type_show()
452 if (hdev->asic_type == ASIC_GOYA) in hl_sysfs_init()
/linux/sound/soc/amd/
A Dacp-pcm-dma.c206 u32 asic_type) in set_acp_sysmem_dma_descriptors() argument
218 switch (asic_type) { in set_acp_sysmem_dma_descriptors()
235 switch (asic_type) { in set_acp_sysmem_dma_descriptors()
332 u32 asic_type) in config_acp_dma() argument
637 if (asic_type != CHIP_STONEY) { in acp_init()
775 switch (intr_data->asic_type) { in acp_dma_open()
783 switch (intr_data->asic_type) { in acp_dma_open()
906 switch (adata->asic_type) { in acp_dma_hw_params()
947 switch (adata->asic_type) { in acp_dma_hw_params()
1119 switch (adata->asic_type) { in acp_dma_new()
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/linux/drivers/gpu/drm/amd/amdgpu/
A Dnbio_v7_4.c114 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_get_rev_id()
187 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_vcn_doorbell_range()
377 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_handle_ras_controller_intr_no_bifring()
388 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_handle_ras_controller_intr_no_bifring()
433 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
445 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring()
466 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_set_ras_controller_irq_state()
511 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_set_ras_err_event_athub_irq_state()
600 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_query_ras_error_count()
610 if (adev->asic_type == CHIP_ALDEBARAN) in nbio_v7_4_query_ras_error_count()
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A Dumc_v6_1.c100 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_clear_error_count_per_channel()
178 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_query_correctable_error_count()
233 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_querry_uncorrectable_error_count()
268 if ((adev->asic_type == CHIP_ARCTURUS) && in umc_v6_1_query_ras_error_count()
285 if ((adev->asic_type == CHIP_ARCTURUS) && in umc_v6_1_query_ras_error_count()
306 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_query_error_address()
383 if ((adev->asic_type == CHIP_ARCTURUS) && in umc_v6_1_query_ras_error_address()
399 if ((adev->asic_type == CHIP_ARCTURUS) && in umc_v6_1_query_ras_error_address()
413 if (adev->asic_type == CHIP_ARCTURUS) { in umc_v6_1_err_cnt_init_per_channel()
A Dgfxhub_v1_1.c52 if (adev->asic_type == CHIP_ALDEBARAN) { in gfxhub_v1_1_get_xgmi_info()
70 switch (adev->asic_type) { in gfxhub_v1_1_get_xgmi_info()
94 if (adev->asic_type == CHIP_ALDEBARAN) { in gfxhub_v1_1_get_xgmi_info()
A Dnbio_v7_2.c62 if (adev->asic_type == CHIP_YELLOW_CARP) in nbio_v7_2_get_rev_id()
76 if (adev->asic_type == CHIP_YELLOW_CARP) in nbio_v7_2_mc_access_enable()
85 if (adev->asic_type == CHIP_YELLOW_CARP) in nbio_v7_2_mc_access_enable()
253 if (adev->asic_type == CHIP_YELLOW_CARP) { in nbio_v7_2_update_medium_grain_light_sleep()
355 if (adev->asic_type == CHIP_YELLOW_CARP) { in nbio_v7_2_init_registers()
A Dvce_v3_0.c305 if (adev->asic_type >= CHIP_STONEY) in vce_v3_0_start()
342 if (adev->asic_type >= CHIP_STONEY) in vce_v3_0_stop()
368 if ((adev->asic_type == CHIP_FIJI) || in vce_v3_0_get_harvest_config()
369 (adev->asic_type == CHIP_STONEY)) in vce_v3_0_get_harvest_config()
389 if ((adev->asic_type == CHIP_POLARIS10) || in vce_v3_0_get_harvest_config()
390 (adev->asic_type == CHIP_POLARIS11) || in vce_v3_0_get_harvest_config()
391 (adev->asic_type == CHIP_POLARIS12) || in vce_v3_0_get_harvest_config()
392 (adev->asic_type == CHIP_VEGAM)) in vce_v3_0_get_harvest_config()
568 if (adev->asic_type >= CHIP_STONEY) { in vce_v3_0_mc_resume()
975 if (adev->asic_type >= CHIP_STONEY) { in vce_v3_0_set_ring_funcs()
A Damdgpu_reset.c39 switch (adev->asic_type) { in amdgpu_reset_init()
54 switch (adev->asic_type) { in amdgpu_reset_fini()
A Ddf_v3_6.c223 if ((adev->asic_type == CHIP_ARCTURUS && in df_v3_6_query_hashes()
225 (adev->asic_type == CHIP_ALDEBARAN && in df_v3_6_query_hashes()
280 if (adev->asic_type == CHIP_ALDEBARAN) { in df_v3_6_get_fb_channel_number()
520 switch (adev->asic_type) { in df_v3_6_pmc_start()
562 switch (adev->asic_type) { in df_v3_6_pmc_stop()
601 switch (adev->asic_type) { in df_v3_6_pmc_get_count()
A Dvi.c105 #define ASIC_IS_P22(asic_type, rid) ((asic_type >= CHIP_POLARIS10) && \ argument
106 (asic_type <= CHIP_POLARIS12) && \
260 switch (adev->asic_type) { in vi_query_video_codecs()
496 switch (adev->asic_type) { in vi_init_golden_registers()
900 switch (adev->asic_type) { in vi_asic_supports_baco()
926 switch (adev->asic_type) { in vi_asic_reset_method()
1143 adev->asic_type < CHIP_POLARIS10) in vi_program_aspm()
1347 switch (adev->asic_type) { in vi_need_full_reset()
1496 switch (adev->asic_type) { in vi_common_early_init()
1991 switch (adev->asic_type) { in vi_common_set_clockgating_state()
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A Damdgpu_acp.c258 switch (adev->asic_type) { in acp_hw_init()
270 switch (adev->asic_type) { in acp_hw_init()
287 switch (adev->asic_type) { in acp_hw_init()
328 adev->acp.acp_cell[0].platform_data = &adev->asic_type; in acp_hw_init()
329 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); in acp_hw_init()
A Dmmhub_v1_0.c453 if (adev->asic_type != CHIP_RAVEN) { in mmhub_v1_0_update_medium_grain_clock_gating()
469 if (adev->asic_type != CHIP_RAVEN) in mmhub_v1_0_update_medium_grain_clock_gating()
486 if (adev->asic_type != CHIP_RAVEN) in mmhub_v1_0_update_medium_grain_clock_gating()
499 if (adev->asic_type != CHIP_RAVEN) in mmhub_v1_0_update_medium_grain_clock_gating()
505 if (adev->asic_type != CHIP_RAVEN && def2 != data2) in mmhub_v1_0_update_medium_grain_clock_gating()
531 switch (adev->asic_type) { in mmhub_v1_0_set_clockgating()
A Damdgpu_uvd.c193 switch (adev->asic_type) { in amdgpu_uvd_sw_init()
284 if (adev->asic_type < CHIP_VEGA20) { in amdgpu_uvd_sw_init()
305 if ((adev->asic_type == CHIP_POLARIS10 || in amdgpu_uvd_sw_init()
306 adev->asic_type == CHIP_POLARIS11) && in amdgpu_uvd_sw_init()
354 switch (adev->asic_type) { in amdgpu_uvd_sw_init()
368 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; in amdgpu_uvd_sw_init()
435 if (adev->asic_type < CHIP_POLARIS10) { in amdgpu_uvd_suspend()
1139 if (adev->asic_type >= CHIP_VEGA10) { in amdgpu_uvd_send_msg()
A Dgfx_v8_0.c740 switch (adev->asic_type) { in gfx_v8_0_init_golden_registers()
972 switch (adev->asic_type) { in gfx_v8_0_init_microcode()
1004 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode()
1024 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode()
1045 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode()
1125 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode()
1147 if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) { in gfx_v8_0_init_microcode()
1701 switch (adev->asic_type) { in gfx_v8_0_gpu_early_init()
1948 switch (adev->asic_type) { in gfx_v8_0_sw_init()
2132 switch (adev->asic_type) { in gfx_v8_0_tiling_mode_table_init()
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A Dnbio_v2_3.c514 if (!((adev->asic_type >= CHIP_NAVI10) && in nbio_v2_3_apply_lc_spc_mode_wa()
515 (adev->asic_type <= CHIP_NAVI12))) in nbio_v2_3_apply_lc_spc_mode_wa()
538 if (adev->asic_type != CHIP_NAVI10) in nbio_v2_3_apply_l1_link_width_reconfig_wa()
550 if (adev->asic_type != CHIP_SIENNA_CICHLID) in nbio_v2_3_clear_doorbell_interrupt()
A Dgmc_v8_0.c132 switch (adev->asic_type) { in gmc_v8_0_init_golden_registers()
229 switch (adev->asic_type) { in gmc_v8_0_init_microcode()
590 switch (adev->asic_type) { in gmc_v8_0_mc_init()
1110 if ((adev->asic_type == CHIP_FIJI) || in gmc_v8_0_sw_init()
1111 (adev->asic_type == CHIP_VEGAM)) in gmc_v8_0_sw_init()
1219 if (adev->asic_type == CHIP_TONGA) { in gmc_v8_0_hw_init()
1225 } else if (adev->asic_type == CHIP_POLARIS11 || in gmc_v8_0_hw_init()
1226 adev->asic_type == CHIP_POLARIS10 || in gmc_v8_0_hw_init()
1227 adev->asic_type == CHIP_POLARIS12) { in gmc_v8_0_hw_init()
1669 switch (adev->asic_type) { in gmc_v8_0_set_clockgating_state()
A Damdgpu_device.c1051 if (adev->asic_type >= CHIP_VEGA10) in amdgpu_device_doorbell_init()
1226 if (adev->asic_type >= CHIP_BONAIRE) in amdgpu_device_resize_fb_bar()
1276 if (adev->asic_type == CHIP_FIJI) { in amdgpu_device_need_post()
1300 if (adev->asic_type >= CHIP_BONAIRE) in amdgpu_device_need_post()
1423 adev->asic_type < CHIP_RAVEN) in amdgpu_device_init_apu_flags()
1426 switch (adev->asic_type) { in amdgpu_device_init_apu_flags()
1902 if (adev->asic_type != CHIP_NAVI12) in amdgpu_device_parse_gpu_info_fw()
1906 switch (adev->asic_type) { in amdgpu_device_parse_gpu_info_fw()
2083 switch (adev->asic_type) { in amdgpu_device_ip_early_init()
3168 switch (asic_type) { in amdgpu_device_asic_has_dc_support()
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A Damdgpu_gmc.c128 if (adev->asic_type >= CHIP_VEGA10) { in amdgpu_gmc_pd_addr()
563 switch (adev->asic_type) { in amdgpu_gmc_tmz_set()
612 switch (adev->asic_type) { in amdgpu_gmc_noretry_set()
684 switch (adev->asic_type) { in amdgpu_gmc_get_vbios_allocations()
817 switch (adev->asic_type) { in amdgpu_gmc_get_reserved_allocation()
A Damdgpu_virt.c53 if (adev->asic_type != CHIP_ALDEBARAN && in amdgpu_virt_init_setting()
54 adev->asic_type != CHIP_ARCTURUS) { in amdgpu_virt_init_setting()
675 switch (adev->asic_type) { in amdgpu_detect_virtualization()
707 switch (adev->asic_type) { in amdgpu_detect_virtualization()
726 DRM_ERROR("Unknown asic type: %d!\n", adev->asic_type); in amdgpu_detect_virtualization()
A Dsi.c992 switch (adev->asic_type) { in si_query_video_codecs()
2044 switch (adev->asic_type) { in si_common_early_init()
2164 switch (adev->asic_type) { in si_init_golden_registers()
2516 if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) { in si_program_aspm()
2565 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) in si_program_aspm()
2572 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) in si_program_aspm()
2751 switch (adev->asic_type) { in si_set_ip_blocks()
A Damdgpu_ras.c546 if (obj->adev->asic_type == CHIP_ALDEBARAN) { in amdgpu_ras_sysfs_read()
2114 if ((adev->asic_type == CHIP_ALDEBARAN) && in amdgpu_ras_recovery_init()
2162 return adev->asic_type == CHIP_VEGA10 || in amdgpu_ras_asic_supported()
2163 adev->asic_type == CHIP_VEGA20 || in amdgpu_ras_asic_supported()
2164 adev->asic_type == CHIP_ARCTURUS || in amdgpu_ras_asic_supported()
2165 adev->asic_type == CHIP_ALDEBARAN || in amdgpu_ras_asic_supported()
2166 adev->asic_type == CHIP_SIENNA_CICHLID; in amdgpu_ras_asic_supported()
2290 if (!adev->ras_enabled || adev->asic_type == CHIP_VEGA10) { in amdgpu_ras_init()
2294 if (!adev->ras_enabled && adev->asic_type == CHIP_VEGA20) { in amdgpu_ras_init()
2312 switch (adev->asic_type) { in amdgpu_ras_init()
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/linux/drivers/gpu/drm/amd/pm/
A Damdgpu_pm.c2047 enum amd_asic_type asic_type = adev->asic_type; in default_attr_update() local
2057 if (asic_type < CHIP_VEGA10) in default_attr_update()
2060 if (asic_type < CHIP_VEGA10 || in default_attr_update()
2065 if (asic_type < CHIP_VEGA20) in default_attr_update()
2081 if (asic_type != CHIP_VEGA10 && in default_attr_update()
2082 asic_type != CHIP_VEGA20 && in default_attr_update()
2083 asic_type != CHIP_ARCTURUS) in default_attr_update()
2089 if (asic_type < CHIP_VEGA12) in default_attr_update()
2092 if (!(asic_type == CHIP_VANGOGH || asic_type == CHIP_SIENNA_CICHLID)) in default_attr_update()
2095 if (!(asic_type == CHIP_VANGOGH || asic_type == CHIP_SIENNA_CICHLID)) in default_attr_update()
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/linux/drivers/gpu/drm/amd/pm/powerplay/
A Dkv_dpm.c774 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_unforce_levels()
1381 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_disable()
1753 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_dpm_powergate_acp()
1934 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_dpm_set_power_state()
1960 if (adev->asic_type == CHIP_MULLINS) in kv_dpm_set_power_state()
2014 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) {
2119 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_highest()
2139 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) in kv_force_dpm_lowest()
2295 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_apply_state_adjust_rules()
2356 if (adev->asic_type == CHIP_KABINI || adev->asic_type == CHIP_MULLINS) { in kv_calculate_nbps_level_settings()
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/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu7_baco.c72 switch (adev->asic_type) { in smu7_baco_set_state()

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