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Searched refs:bw_ctx (Results 1 – 25 of 34) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c1861 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
1864 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn31_calculate_wm_and_dlg_fp()
1892 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
1901 …context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn31_calculate_wm_and_dlg_fp()
1914 …context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
1933 …context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
1951 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn31_calculate_wm_and_dlg_fp()
1962 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
1963 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
1964 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c2929 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
3116 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
3117 context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000; in dcn20_calculate_dlg_params()
3118 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
3119 context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16; in dcn20_calculate_dlg_params()
3125 context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000; in dcn20_calculate_dlg_params()
3127 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
3156 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dcn20_calculate_dlg_params()
3157 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dcn20_calculate_dlg_params()
3173 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, in dcn20_calculate_dlg_params()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c2137 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_calculate_wm_and_dlg_fp()
2156 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_calculate_wm_and_dlg_fp()
2160 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_calculate_wm_and_dlg_fp()
2163 …context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_calculate_wm_and_dlg_fp()
2211 …context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_calculate_wm_and_dlg_fp()
2215 …context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn30_calculate_wm_and_dlg_fp()
2218 …context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, p… in dcn30_calculate_wm_and_dlg_fp()
2224 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; in dcn30_calculate_wm_and_dlg_fp()
2234 …context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_calculate_wm_and_dlg_fp()
2247 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn30_calculate_wm_and_dlg_fp()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce112/
A Ddce112_resource.c902 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
910 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
911 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
927 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
928 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
943 context->bw_ctx.bw.dce.stutter_mode_enable, in dce112_validate_bandwidth()
947 context->bw_ctx.bw.dce.all_displays_in_sync, in dce112_validate_bandwidth()
948 context->bw_ctx.bw.dce.dispclk_khz, in dce112_validate_bandwidth()
949 context->bw_ctx.bw.dce.sclk_khz, in dce112_validate_bandwidth()
950 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce112_validate_bandwidth()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_debug.c352 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
353 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
354 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
355 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
356 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
357 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
360 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
361 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
362 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
364 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
[all …]
A Ddc.c1795 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); in dc_commit_state_no_check()
1797 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_commit_state_no_check()
1927 TRACE_DCN_CLOCK_STATE(&context->bw_ctx.bw.dcn.clk); in dc_post_update_surfaces_to_stream()
1929 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_post_update_surfaces_to_stream()
1958 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
3206 TRACE_DCE_CLOCK_STATE(&context->bw_ctx.bw.dce); in dc_commit_updates_for_stream()
3321 dc->current_state->bw_ctx.dml = *dml; in dc_set_power_state()
3487 info->dppClock = (unsigned int)state->bw_ctx.bw.dcn.clk.dppclk_khz; in get_clock_requirements_for_state()
3488 info->socClock = (unsigned int)state->bw_ctx.bw.dcn.clk.socclk_khz; in get_clock_requirements_for_state()
3490 info->fClock = (unsigned int)state->bw_ctx.bw.dcn.clk.fclk_khz; in get_clock_requirements_for_state()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/calcs/
A Ddcn_calcs.c631 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
632 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
635 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1172 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1173 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1174 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1188 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth()
1190 context->bw_ctx.bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth()
1194 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / in dcn_validate_bandwidth()
1199 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/dce110/
A Ddce110_resource.c980 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
990 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
991 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1007 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1008 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1023 context->bw_ctx.bw.dce.stutter_mode_enable, in dce110_validate_bandwidth()
1027 context->bw_ctx.bw.dce.all_displays_in_sync, in dce110_validate_bandwidth()
1028 context->bw_ctx.bw.dce.dispclk_khz, in dce110_validate_bandwidth()
1029 context->bw_ctx.bw.dce.sclk_khz, in dce110_validate_bandwidth()
1030 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce110_validate_bandwidth()
[all …]
A Ddce110_hw_sequencer.c1916 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1917 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1918 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1919 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1925 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1926 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1927 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c352 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn301_calculate_wm_and_dlg()
353 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg()
357 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn301_calculate_wm_and_dlg()
358 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg()
362 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn301_calculate_wm_and_dlg()
363 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg()
368 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn301_calculate_wm_and_dlg()
369 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg()
375 …pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cn… in dcn301_calculate_wm_and_dlg()
379 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz; in dcn301_calculate_wm_and_dlg()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c1111 patch_bounding_box(dc, &context->bw_ctx.dml.soc); in dcn21_calculate_wm()
1118 …ipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context-… in dcn21_calculate_wm()
1122 … context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn21_calculate_wm()
1131 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_… in dcn21_calculate_wm()
1162 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_calculate_wm()
1167 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_calculate_wm()
1172 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_calculate_wm()
1178 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_calculate_wm()
1291 … context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; in dcn21_fast_validate_bw()
1316 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clk_mgr.c227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
617 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
619 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
625 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
632 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
645 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
676 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
703 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
730 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
A Ddcn201_clk_mgr.c81 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks_vbios()
127 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn201_update_clocks()
201 if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz) in dcn201_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_hw_sequencer_debug.c475 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_get_clock_states()
476 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in dcn10_get_clock_states()
477 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
478 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_get_clock_states()
479 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_get_clock_states()
480 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_get_clock_states()
A Ddcn10_hw_sequencer.c459 dc->current_state->bw_ctx.bw.dcn.clk.dcfclk_khz, in dcn10_log_hw_state()
461 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
462 dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz, in dcn10_log_hw_state()
464 dc->current_state->bw_ctx.bw.dcn.clk.fclk_khz, in dcn10_log_hw_state()
465 dc->current_state->bw_ctx.bw.dcn.clk.socclk_khz); in dcn10_log_hw_state()
2649 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn10_update_dchubp_dpp()
2654 context->bw_ctx.bw.dcn.clk.dppclk_khz <= in dcn10_update_dchubp_dpp()
2972 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_prepare_bandwidth()
2981 &context->bw_ctx.bw.dcn.watermarks, in dcn10_prepare_bandwidth()
3005 context->bw_ctx.bw.dcn.clk.phyclk_khz = 0; in dcn10_optimize_bandwidth()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c214 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks()
350 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in dcn2_update_clocks_fpga()
458 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
461 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
464 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
467 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
A Ddce_clk_mgr.c208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
401 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
A Ddce120_clk_mgr.c91 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/dce100/
A Ddce100_resource.c851 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce100_validate_bandwidth()
852 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; in dce100_validate_bandwidth()
854 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce100_validate_bandwidth()
855 context->bw_ctx.bw.dce.yclk_khz = 0; in dce100_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
A Ddce60_clk_mgr.c126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/dce60/
A Ddce60_resource.c880 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce60_validate_bandwidth()
881 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; in dce60_validate_bandwidth()
883 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce60_validate_bandwidth()
884 context->bw_ctx.bw.dce.yclk_khz = 0; in dce60_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/dce80/
A Ddce80_resource.c885 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce80_validate_bandwidth()
886 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ; in dce80_validate_bandwidth()
888 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce80_validate_bandwidth()
889 context->bw_ctx.bw.dce.yclk_khz = 0; in dce80_validate_bandwidth()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
A Ddce112_clk_mgr.c201 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
A Drv1_clk_mgr.c197 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk; in rv1_update_clocks()

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