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Searched refs:c15 (Results 1 – 25 of 28) sorted by relevance

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/linux/arch/arm/mm/
A Dproc-v7.S195 mrc p15, 0, r4, c15, c0, 1 @ Diagnostic register
196 mrc p15, 0, r5, c15, c0, 0 @ Power register
206 mcrne p15, 0, r4, c15, c0, 1 @ No, so restore it
456 mrc p15, 1, r0, c15, c1, 1
460 mcr p15, 1, r0, c15, c1, 1
463 mrc p15, 1, r0, c15, c1, 2
466 mcr p15, 1, r0, c15, c1, 2
469 mrc p15, 1, r0, c15, c2, 0
475 mcr p15, 1, r0, c15, c2, 0
478 mrc p15, 1, r0, c15, c1, 0
[all …]
A Dproc-feroceon.S68 mcr p15, 1, r0, c15, c9, 0 @ clean L2
252 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
253 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
298 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
299 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
330 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
331 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
361 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
362 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
445 1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
[all …]
A Dproc-sa110.S37 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
45 mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching
92 mcr p15, 0, ip, c15, c2, 2 @ disable clock switching
98 mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned
102 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
A Dproc-sa1100.S41 mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching
53 mcr p15, 0, ip, c15, c2, 2 @ Disable clock switching
108 mcr p15, 0, r0, c15, c2, 2 @ disable clock switching
110 mcr p15, 0, r0, c15, c8, 2 @ wait for interrupt
112 mcr p15, 0, r0, c15, c1, 2 @ enable clock switching
A Dcache-v6.S71 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
179 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate unified line
222 mcrne p15, 0, r1, c7, c15, 1 @ clean & invalidate unified line
279 mcr p15, 0, r0, c7, c15, 1 @ clean & invalidate line
A Dproc-v6.S155 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
207 mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
A Dproc-xsc3.S417 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
435 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
458 mcr p15, 0, r0, c15, c1, 0 @ write CP access register
A Dproc-xscale.S533 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
549 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
566 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes
A Dproc-mohawk.S346 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
364 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
A Dproc-arm925.S433 mcr p15, 0, r0, c15, c1, 0 @ write TI config register
444 mcr p15, 7, r0, c15, c0, 0
/linux/arch/arm/mach-iop32x/include/mach/
A Dentry-macro.S11 mrc p15, 0, \tmp, c15, c1, 0
13 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
14 mrc p15, 0, \tmp, c15, c1, 0
27 mrc p15, 0, \tmp1, c15, c1, 0
30 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
/linux/arch/arm/mach-sunxi/
A Dheadsmp.S37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
/linux/arch/arm/include/asm/hardware/
A Dcp14.h72 #define RCP14_DBGBVR15() MRC14(0, c0, c15, 4)
88 #define RCP14_DBGBCR15() MRC14(0, c0, c15, 5)
104 #define RCP14_DBGWVR15() MRC14(0, c0, c15, 6)
120 #define RCP14_DBGWCR15() MRC14(0, c0, c15, 7)
137 #define RCP14_DBGBXVR15() MRC14(0, c1, c15, 1)
288 #define RCP14_ETMVDCR3() MRC14(1, c0, c15, 0)
304 #define RCP14_ETMACVR15() MRC14(1, c0, c15, 1)
320 #define RCP14_ETMACTR15() MRC14(1, c0, c15, 2)
352 #define RCP14_ETMCNTVR3() MRC14(1, c0, c15, 5)
383 #define RCP14_ETMAUXCR() MRC14(1, c0, c15, 7)
[all …]
/linux/arch/arm/mach-socfpga/
A Dself-refresh.S49 mrc p15, 0, r2, c15, c0, 0
51 mcr p15, 0, r2, c15, c0, 0
116 mrc p15, 0, r2, c15, c0, 0
118 mcr p15, 0, r2, c15, c0, 0
/linux/arch/arm/kernel/
A Diwmmxt.S74 XSC(mrc p15, 0, r2, c15, c1, 0)
82 XSC(mcr p15, 0, r2, c15, c1, 0)
211 XSC(mrc p15, 0, r4, c15, c1, 0)
213 XSC(mcr p15, 0, r4, c15, c1, 0)
226 XSC(mcr p15, 0, r4, c15, c1, 0)
323 XSC(mrc p15, 0, r1, c15, c1, 0)
338 XSC(mcr p15, 0, r1, c15, c1, 0)
/linux/arch/arm/mach-tegra/
A Dreset-handler.S158 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
161 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
171 mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
174 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
/linux/arch/s390/kernel/
A Dtext_amode31.S95 stctg %c0,%c15,0(%r4)
124 lctlg %c0,%c15,0(%r4)
A Dreipl.S31 stctg %c0,%c15,0(%r1)
/linux/arch/arm/mach-imx/
A Dheadsmp.S19 mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
/linux/tools/perf/arch/s390/include/
A Ddwarf-regs-table.h45 REG_DWARFNUM_NAME(c15, 47),
/linux/arch/arm/mach-mvebu/
A Dpmsu_ll.S17 mrc p15, 4, r1, c15, c0 @ get SCU base address
/linux/drivers/gpu/drm/vc4/
A Dvc4_hvs.c114 c9, c10, c11, c12, c13, c14, c15) \ argument
120 VC4_PPF_FILTER_WORD(c15, c15, 0)}
/linux/arch/arm/mach-sa1100/
A Dsleep.S34 mcr p15, 0, r1, c15, c2, 2
/linux/arch/arm/include/debug/
A Dbrcmstb.S77 mrc p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR
/linux/arch/s390/boot/
A Dhead.S308 lctlg %c0,%c15,.Lctl-.LPG0(%r13) # load control registers
355 stctg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r8)

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