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Searched refs:cache_line_size (Results 1 – 25 of 63) sorted by relevance

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/linux/arch/mips/mm/
A Dpage.c100 static int cache_line_size; variable
228 max(cache_line_size >> 1, in set_prefetch_parameters()
310 off = cache_line_size ? min(8, pref_bias_clear_store / cache_line_size) in build_clear_page()
311 * cache_line_size : 0; in build_clear_page()
314 off -= cache_line_size; in build_clear_page()
463 off = cache_line_size ? min(8, pref_bias_copy_load / cache_line_size) * in build_copy_page()
464 cache_line_size : 0; in build_copy_page()
467 off -= cache_line_size; in build_copy_page()
469 off = cache_line_size ? min(8, pref_bias_copy_store / cache_line_size) * in build_copy_page()
470 cache_line_size : 0; in build_copy_page()
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/linux/tools/perf/util/
A Dcacheline.c6 #define cache_line_size(cacheline_sizep) *cacheline_sizep = sysconf(_SC_LEVEL1_DCACHE_LINESIZE) macro
10 static void cache_line_size(int *cacheline_sizep) in cache_line_size() function
22 cache_line_size(&size); in cacheline_size()
/linux/drivers/net/ethernet/mellanox/mlx5/core/
A Dalloc.c183 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_pgdir()
212 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_alloc_db_from_pgdir()
224 offset = db->index * cache_line_size(); in mlx5_alloc_db_from_pgdir()
271 u32 db_per_page = PAGE_SIZE / cache_line_size(); in mlx5_db_free()
/linux/arch/arm64/kernel/
A Dcacheinfo.c20 int cache_line_size(void) in cache_line_size() function
27 EXPORT_SYMBOL_GPL(cache_line_size);
/linux/drivers/s390/cio/
A Dairq.c141 if ((cache_line_size() * BITS_PER_BYTE) < bits in airq_iv_create()
306 cache_line_size(), in airq_init()
307 cache_line_size(), PAGE_SIZE); in airq_init()
/linux/drivers/infiniband/sw/rxe/
A Drxe_queue.c77 if (elem_size < cache_line_size()) in rxe_queue_init()
78 elem_size = cache_line_size(); in rxe_queue_init()
/linux/include/linux/
A Dcache.h85 #define cache_line_size() L1_CACHE_BYTES macro
A Dpci-epf.h55 u8 cache_line_size; member
/linux/drivers/scsi/cxlflash/
A Dcommon.h173 } __aligned(cache_line_size());
228 } __aligned(cache_line_size());
A Dsislite.h480 char carea[cache_line_size()]; /* 128B each */
/linux/arch/arc/include/asm/
A Dcache.h51 #define cache_line_size() SMP_CACHE_BYTES macro
/linux/arch/um/include/asm/
A Dprocessor-generic.h106 #define cache_line_size() (boot_cpu_data.cache_alignment) macro
/linux/arch/arm64/include/asm/
A Dcache.h94 int cache_line_size(void);
/linux/Documentation/PCI/endpoint/function/binding/
A Dpci-test.rst18 cache_line_size don't care
A Dpci-ntb.rst18 cache_line_size don't care
/linux/Documentation/PCI/endpoint/
A Dpci-endpoint-cfs.rst68 ... cache_line_size
132 | cache_line_size
/linux/drivers/pci/endpoint/
A Dpci-ep-cfs.c425 PCI_EPF_HEADER_R(cache_line_size)
426 PCI_EPF_HEADER_W_u8(cache_line_size)
443 CONFIGFS_ATTR(pci_epf_, cache_line_size);
/linux/drivers/pci/
A Dpci-acpi.c124 u8 cache_line_size; /* Not applicable to PCIe */ member
132 .cache_line_size = 8,
151 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size); in program_hpx_type0()
186 hpx0->cache_line_size = fields[2].integer.value; in decode_type0_hpx_record()
730 hpx0.cache_line_size = fields[0].integer.value; in acpi_run_hpp()
A Dpci-bridge-emul.h14 u8 cache_line_size; member
A Dpci-bridge-emul.c270 bridge->conf.cache_line_size = 0x10; in pci_bridge_emul_init()
/linux/tools/virtio/ringtest/
A Dptr_ring.c14 #define cache_line_size() SMP_CACHE_BYTES macro
/linux/arch/powerpc/kernel/
A Deeh_pe.c53 alloc_size = ALIGN(alloc_size, cache_line_size()); in eeh_pe_alloc()
68 cache_line_size()); in eeh_pe_alloc()
/linux/drivers/gpu/drm/amd/amdkfd/
A Dkfd_crat.h166 uint16_t cache_line_size; member
/linux/drivers/staging/vc04_services/interface/vchiq_arm/
A Dvchiq_arm.c72 const unsigned int cache_line_size; member
77 .cache_line_size = 32,
81 .cache_line_size = 64,
479 g_cache_line_size = drvdata->cache_line_size; in vchiq_platform_init()
/linux/include/uapi/rdma/
A Dmlx5-abi.h137 __u32 cache_line_size; member

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