| /linux/tools/perf/Documentation/ |
| A D | perf-c2c.txt | 20 you to track down the cacheline contentions.
82 Specify sorting fields for single cacheline display.
159 - sort all the data based on the cacheline address
160 - store access details for each cacheline
166 2) offsets details for each cacheline
172 - zero based index to identify the cacheline
175 - cacheline address (hex number)
178 - cacheline percentage of all Remote/Local HITM accesses
261 User can specify how to sort offsets for cacheline.
264 output fields set for cacheline offsets output:
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| A D | tips.txt | 37 To report cacheline events from previous recording: perf c2c report
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| A D | perf-report.txt | 157 - dcacheline: the cacheline the data address is on at the time of the sample
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| /linux/drivers/gpu/drm/i915/gt/ |
| A D | intel_ring.h | 111 #define cacheline(a) round_down(a, CACHELINE_BYTES) in assert_ring_tail_valid() macro
112 GEM_BUG_ON(cacheline(tail) == cacheline(head) && tail < head); in assert_ring_tail_valid()
113 #undef cacheline in assert_ring_tail_valid()
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| A D | selftest_timeline.c | 95 unsigned long cacheline; in __mock_hwsp_timeline() local
108 cacheline = hwsp_cacheline(tl); in __mock_hwsp_timeline()
109 err = radix_tree_insert(&state->cachelines, cacheline, tl); in __mock_hwsp_timeline()
113 cacheline); in __mock_hwsp_timeline()
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| /linux/drivers/soc/qcom/ |
| A D | smem.c | 154 __le32 cacheline; member
271 size_t cacheline[SMEM_HOST_COUNT]; member
289 size_t cacheline) in phdr_to_first_cached_entry() argument
323 cached_entry_next(struct smem_private_entry *e, size_t cacheline) in cached_entry_next() argument
327 return p - le32_to_cpu(e->size) - ALIGN(sizeof(*e), cacheline); in cached_entry_next()
515 size_t cacheline, in qcom_smem_get_private() argument
541 e = phdr_to_first_cached_entry(phdr, cacheline); in qcom_smem_get_private()
556 e = cached_entry_next(e, cacheline); in qcom_smem_get_private()
599 cacheln = __smem->cacheline[host]; in qcom_smem_get()
811 smem->global_cacheline = le32_to_cpu(entry->cacheline); in qcom_smem_set_global_partition()
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| /linux/include/asm-generic/ |
| A D | vmlinux.lds.h | 1057 #define PERCPU_INPUT(cacheline) \ argument
1062 . = ALIGN(cacheline); \
1064 . = ALIGN(cacheline); \
1094 #define PERCPU_VADDR(cacheline, vaddr, phdr) \ argument
1097 PERCPU_INPUT(cacheline) \
1113 #define PERCPU_SECTION(cacheline) \ argument
1117 PERCPU_INPUT(cacheline) \
1139 #define RW_DATA(cacheline, pagealigned, inittask) \ argument
1145 CACHELINE_ALIGNED_DATA(cacheline) \
1146 READ_MOSTLY_DATA(cacheline) \
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| /linux/drivers/md/bcache/ |
| A D | bset.c | 526 unsigned int cacheline, in cacheline_to_bkey() argument
529 return ((void *) t->data) + cacheline * BSET_CACHELINE + offset * 8; in cacheline_to_bkey()
538 unsigned int cacheline, in bkey_to_cacheline_offset() argument
541 return (u64 *) k - (u64 *) cacheline_to_bkey(t, cacheline, 0); in bkey_to_cacheline_offset()
558 static struct bkey *table_to_bkey(struct bset_tree *t, unsigned int cacheline) in table_to_bkey() argument
560 return cacheline_to_bkey(t, cacheline, t->prev[cacheline]); in table_to_bkey()
694 unsigned int j, cacheline = 1; in bch_bset_build_written_tree() local
715 while (bkey_to_cacheline(t, k) < cacheline) { in bch_bset_build_written_tree()
721 t->tree[j].m = bkey_to_cacheline_offset(t, cacheline++, k); in bch_bset_build_written_tree()
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| /linux/scripts/gcc-plugins/ |
| A D | Kconfig | 77 bool "Use cacheline-aware structure randomization"
82 best effort at restricting randomization to cacheline-sized
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| /linux/Documentation/sparc/ |
| A D | adi.rst | 35 size is same as cacheline size which is 64 bytes. A task that sets ADI
103 the corresponding cacheline, a memory corruption trap occurs. By
123 the corresponding cacheline, a memory corruption trap occurs. If
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| /linux/kernel/ |
| A D | Kconfig.hz | 14 contention and cacheline bounces as a result of timer interrupts.
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| /linux/arch/sparc/kernel/ |
| A D | prom_irqtrans.c | 355 static unsigned char cacheline[64] in tomatillo_wsync_handler() local
366 "i" (FPRS_FEF), "r" (&cacheline[0]), in tomatillo_wsync_handler()
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| A D | cherrs.S | 203 sub %g1, %g2, %g1 ! Move down 1 cacheline
215 subcc %g1, %g2, %g1 ! Next cacheline
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| /linux/Documentation/translations/zh_CN/core-api/ |
| A D | cachetlb.rst | 195 加载到不同的cacheline中就会出现别名现象。
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| /linux/arch/parisc/kernel/ |
| A D | perf_asm.S | 132 ; Cacheline start (32-byte cacheline)
145 ; Cacheline start (32-byte cacheline)
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| /linux/Documentation/locking/ |
| A D | mutex-design.rst | 55 cacheline bouncing that common test-and-set spinlock implementations
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| /linux/Documentation/driver-api/ |
| A D | edac.rst | 46 lockstep is enabled, the cacheline is doubled, but it generally brings
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| /linux/tools/perf/util/ |
| A D | Build | 5 perf-y += cacheline.o
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| /linux/Documentation/ |
| A D | atomic_t.txt | 358 loop body. As a result there is no guarantee what so ever the cacheline
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| /linux/Documentation/networking/device_drivers/ethernet/amazon/ |
| A D | ena.rst | 28 and CPU cacheline optimized data placement.
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| /linux/drivers/edac/ |
| A D | Kconfig | 95 - inject_section (0..3, 16-byte section of 64-byte cacheline),
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| /linux/Documentation/core-api/ |
| A D | dma-api-howto.rst | 137 buffers were cacheline-aligned. Without that, you'd see cacheline
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| /linux/drivers/char/ |
| A D | Kconfig | 116 of threads across a large system which avoids bouncing a cacheline
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| /linux/drivers/scsi/aic7xxx/ |
| A D | aic7xxx.seq | 754 * We fetch a "cacheline aligned" and sized amount of data
758 * cacheline size is unknown.
795 * If the ending address is on a cacheline boundary,
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| /linux/Documentation/filesystems/ |
| A D | path-lookup.txt | 32 common path elements causes lock and cacheline queueing.
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