| /linux/tools/cgroup/ |
| A D | memcg_slabinfo.py | 184 caches = {}
203 caches[addr] = cache
215 for addr in caches:
217 cache_show(caches[addr], cfg, stats[addr])
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| /linux/Documentation/block/ |
| A D | writeback_cache_control.rst | 9 write back caches. That means the devices signal I/O completion to the
60 devices with volatile caches need to implement the support for these
67 For devices that do not support volatile write caches there is no driver
70 requests that have a payload. For devices with volatile write caches the
71 driver needs to tell the block layer that it supports flushing caches by
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| /linux/arch/arm/mm/ |
| A D | proc-arm720.S | 46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
108 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
136 mcr p15, 0, r0, c7, c7, 0 @ invalidate caches
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| A D | proc-sa110.S | 49 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
162 mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-fa526.S | 39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
58 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
137 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-arm926.S | 53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
69 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
404 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
417 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
425 mov r0, #4 @ disable write-back on caches explicitly
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| A D | proc-arm920.S | 61 mcr p15, 0, r0, c1, c0, 0 @ disable caches
77 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
389 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
402 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-mohawk.S | 44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
359 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
378 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches
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| A D | proc-sa1100.S | 57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
73 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
201 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-arm925.S | 84 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
436 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
443 mov r0, #4 @ disable write-back on caches explicitly
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| A D | proc-arm740.S | 40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
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| A D | proc-arm922.S | 63 mcr p15, 0, r0, c1, c0, 0 @ disable caches
79 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
380 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-arm1020e.S | 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
415 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-arm1022.S | 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
408 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-arm1026.S | 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
397 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-xsc3.S | 92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
430 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
450 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
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| A D | proc-arm1020.S | 69 mcr p15, 0, r0, c1, c0, 0 @ disable caches
85 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
433 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-feroceon.S | 75 mcr p15, 0, r0, c1, c0, 0 @ disable caches
91 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
520 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
533 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
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| A D | proc-xscale.S | 128 mcr p15, 0, r0, c1, c0, 0 @ disable caches
156 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
547 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
561 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
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| /linux/arch/arm/boot/compressed/ |
| A D | head-xscale.S | 28 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
30 @ disabling MMU and caches
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| /linux/arch/openrisc/ |
| A D | Kconfig | 78 bool "Have write through data caches"
81 Select this if your implementation features write through data caches.
83 caches at relevant times. Most OpenRISC implementations support write-
84 through data caches.
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| /linux/drivers/acpi/numa/ |
| A D | hmat.c | 67 struct list_head caches; member
142 INIT_LIST_HEAD(&target->caches); in alloc_memory_target()
415 list_add_tail(&tcache->node, &target->caches); in hmat_parse_cache()
685 list_for_each_entry(tcache, &target->caches, node) in hmat_register_target_cache()
786 list_for_each_entry_safe(tcache, cnext, &target->caches, node) { in hmat_free_structures()
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| /linux/Documentation/filesystems/nfs/ |
| A D | rpc-cache.rst | 13 a wide variety of values to be caches.
15 There are a number of caches that are similar in structure though
17 of common code for managing these caches.
19 Examples of caches that are likely to be needed are:
105 includes it on a list of caches that will be regularly
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| /linux/tools/perf/util/ |
| A D | header.c | 1186 caches[cnt++] = c; in build_caches()
1199 struct cpu_cache_level caches[max_caches]; in write_cache() local
1203 ret = build_caches(caches, &cnt); in write_cache()
1218 struct cpu_cache_level *c = &caches[i]; in write_cache()
1244 cpu_cache_level__free(&caches[i]); in write_cache()
2799 struct cpu_cache_level *caches; in process_cache() local
2811 caches = zalloc(sizeof(*caches) * cnt); in process_cache()
2812 if (!caches) in process_cache()
2838 caches[i] = c; in process_cache()
2841 ff->ph->env.caches = caches; in process_cache()
[all …]
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| /linux/Documentation/core-api/ |
| A D | cachetlb.rst | 121 us to properly handle systems whose caches are strict and require
129 indexed caches which must be flushed when virtual-->physical
131 indexed physically tagged caches of IA32 processors have no need to
132 implement these interfaces since the caches are fully synchronized
140 the caches. That is, after running, there will be no cache
149 the caches. That is, after running, there will be no cache
156 optimizations for VIPT caches.
|