/linux/drivers/clk/ingenic/ |
A D | cgu.c | 84 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate() local 195 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_set_rate() local 235 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_enable() local 266 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_disable() local 284 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_is_enabled() local 312 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_get_parent() local 338 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_parent() local 386 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_recalc_rate() local 504 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_clk_set_rate() local 659 ingenic_clk->cgu = cgu; in ingenic_register_clock() [all …]
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A D | Makefile | 2 obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o 3 obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o 4 obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o 5 obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o 6 obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o 7 obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o 8 obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o 9 obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o
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A D | jz4780-cgu.c | 103 static struct ingenic_cgu *cgu; variable 173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate() 180 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate() 226 struct ingenic_cgu *cgu = ingenic_clk->cgu; in jz4780_core1_enable() local 232 spin_lock_irqsave(&cgu->lock, flags); in jz4780_core1_enable() 234 lcr = readl(cgu->base + CGU_REG_LCR); in jz4780_core1_enable() 236 writel(lcr, cgu->base + CGU_REG_LCR); in jz4780_core1_enable() 242 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_core1_enable() 778 cgu = ingenic_cgu_new(jz4780_cgu_clocks, in jz4780_cgu_init() 780 if (!cgu) { in jz4780_cgu_init() [all …]
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A D | x1000-cgu.c | 61 static struct ingenic_cgu *cgu; variable 69 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate() 121 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate() 123 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate() 126 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate() 128 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate() 134 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_enable() 461 cgu = ingenic_cgu_new(x1000_cgu_clocks, in x1000_cgu_init() 463 if (!cgu) { in x1000_cgu_init() 468 retval = ingenic_cgu_register_clocks(cgu); in x1000_cgu_init() [all …]
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A D | x1830-cgu.c | 55 static struct ingenic_cgu *cgu; variable 59 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_enable() 60 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_enable() 69 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_disable() 70 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_disable() 78 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_is_enabled() 79 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_is_enabled() 442 cgu = ingenic_cgu_new(x1830_cgu_clocks, in x1830_cgu_init() 444 if (!cgu) { in x1830_cgu_init() 449 retval = ingenic_cgu_register_clocks(cgu); in x1830_cgu_init() [all …]
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A D | jz4770-cgu.c | 49 static struct ingenic_cgu *cgu; variable 53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable() 54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable() 63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable() 64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable() 72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled() 73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled() 438 cgu = ingenic_cgu_new(jz4770_cgu_clocks, in jz4770_cgu_init() 440 if (!cgu) { in jz4770_cgu_init() 445 retval = ingenic_cgu_register_clocks(cgu); in jz4770_cgu_init() [all …]
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A D | jz4725b-cgu.c | 33 static struct ingenic_cgu *cgu; variable 251 cgu = ingenic_cgu_new(jz4725b_cgu_clocks, in jz4725b_cgu_init() 253 if (!cgu) { in jz4725b_cgu_init() 258 retval = ingenic_cgu_register_clocks(cgu); in jz4725b_cgu_init() 262 ingenic_cgu_register_syscore_ops(cgu); in jz4725b_cgu_init()
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A D | jz4740-cgu.c | 48 static struct ingenic_cgu *cgu; variable 248 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init() 250 if (!cgu) { in jz4740_cgu_init() 255 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init() 259 ingenic_cgu_register_syscore_ops(cgu); in jz4740_cgu_init()
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A D | jz4760-cgu.c | 407 struct ingenic_cgu *cgu; in jz4760_cgu_init() local 410 cgu = ingenic_cgu_new(jz4760_cgu_clocks, in jz4760_cgu_init() 412 if (!cgu) { in jz4760_cgu_init() 417 retval = ingenic_cgu_register_clocks(cgu); in jz4760_cgu_init() 421 ingenic_cgu_register_syscore_ops(cgu); in jz4760_cgu_init()
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/linux/Documentation/devicetree/bindings/clock/ |
A D | ingenic,cgu.yaml | 23 - ingenic,jz4740-cgu 24 - ingenic,jz4725b-cgu 25 - ingenic,jz4760-cgu 26 - ingenic,jz4760b-cgu 27 - ingenic,jz4770-cgu 28 - ingenic,jz4780-cgu 29 - ingenic,x1000-cgu 30 - ingenic,x1830-cgu 52 - ingenic,jz4740-cgu 58 - ingenic,x1000-cgu [all …]
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A D | lpc1850-ccu.txt | 47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, 48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, 49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, 50 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; 61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, 62 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, 63 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, 64 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
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A D | intel,cgu-lgm.yaml | 4 $id: http://devicetree.org/schemas/clock/intel,cgu-lgm.yaml# 23 const: intel,cgu-lgm 40 cgu: clock-controller@e0200000 { 41 compatible = "intel,cgu-lgm";
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/linux/arch/mips/boot/dts/ingenic/ |
A D | jz4740.dtsi | 19 clocks = <&cgu JZ4740_CLK_CCLK>; 53 cgu: jz4740-cgu@10000000 { label 72 clocks = <&cgu JZ4740_CLK_RTC>, 73 <&cgu JZ4740_CLK_EXT>, 74 <&cgu JZ4740_CLK_PCLK>, 75 <&cgu JZ4740_CLK_TCU>; 114 clocks = <&cgu JZ4740_CLK_RTC>; 196 <&cgu JZ4740_CLK_I2S>, 197 <&cgu JZ4740_CLK_EXT>, 198 <&cgu JZ4740_CLK_PLL_HALF>; [all …]
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A D | jz4770.dtsi | 19 clocks = <&cgu JZ4770_CLK_CCLK>; 53 cgu: jz4770-cgu@10000000 { label 84 clocks = <&cgu JZ4770_CLK_RTC>, 85 <&cgu JZ4770_CLK_EXT>, 86 <&cgu JZ4770_CLK_PCLK>; 241 clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>, 242 <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>; 258 clocks = <&cgu JZ4770_CLK_AIC>; 392 <&cgu JZ4770_CLK_GPU>, 393 <&cgu JZ4770_CLK_GPU>; [all …]
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A D | jz4725b.dtsi | 19 clocks = <&cgu JZ4725B_CLK_CCLK>; 53 cgu: clock-controller@10000000 { label 54 compatible = "ingenic,jz4725b-cgu"; 72 clocks = <&cgu JZ4725B_CLK_RTC>, 73 <&cgu JZ4725B_CLK_EXT>, 74 <&cgu JZ4725B_CLK_PCLK>, 75 <&cgu JZ4725B_CLK_TCU>; 123 clocks = <&cgu JZ4725B_CLK_RTC>; 202 <&cgu JZ4725B_CLK_I2S>, 203 <&cgu JZ4725B_CLK_EXT>, [all …]
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A D | jz4780.dtsi | 20 clocks = <&cgu JZ4780_CLK_CPU>; 29 clocks = <&cgu JZ4780_CLK_CORE1>; 63 cgu: jz4780-cgu@10000000 { label 79 clocks = <&cgu JZ4780_CLK_OTG1>; 105 clocks = <&cgu JZ4780_CLK_RTCLK>, 106 <&cgu JZ4780_CLK_EXCLK>, 107 <&cgu JZ4780_CLK_PCLK>; 156 clocks = <&cgu JZ4780_CLK_RTCLK>; 267 clocks = <&cgu JZ4780_CLK_SSI0>; 534 clocks = <&cgu JZ4780_CLK_BCH>; [all …]
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A D | x1000.dtsi | 20 clocks = <&cgu X1000_CLK_CPU>; 54 cgu: x1000-cgu@10000000 { label 96 clocks = <&cgu X1000_CLK_OST>; 112 clocks = <&cgu X1000_CLK_RTCLK>, 113 <&cgu X1000_CLK_EXCLK>, 114 <&cgu X1000_CLK_PCLK>; 139 clocks = <&cgu X1000_CLK_RTCLK>; 258 clocks = <&cgu X1000_CLK_I2C0>; 272 clocks = <&cgu X1000_CLK_I2C1>; 352 clocks = <&cgu X1000_CLK_MAC>; [all …]
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A D | x1830.dtsi | 20 clocks = <&cgu X1830_CLK_CPU>; 54 cgu: x1830-cgu@10000000 { label 89 clocks = <&cgu X1830_CLK_OST>; 105 clocks = <&cgu X1830_CLK_RTCLK>, 106 <&cgu X1830_CLK_EXCLK>, 107 <&cgu X1830_CLK_PCLK>; 132 clocks = <&cgu X1830_CLK_RTCLK>; 238 clocks = <&cgu X1830_CLK_SMB0>; 252 clocks = <&cgu X1830_CLK_SMB1>; 341 clocks = <&cgu X1830_CLK_MAC>; [all …]
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A D | gcw0.dts | 443 &cgu { 454 <&cgu JZ4770_CLK_PLL1>, 455 <&cgu JZ4770_CLK_GPU>, 456 <&cgu JZ4770_CLK_RTC>, 457 <&cgu JZ4770_CLK_UHC>, 463 <&cgu JZ4770_CLK_PLL0>, 464 <&cgu JZ4770_CLK_OSC32K>, 465 <&cgu JZ4770_CLK_PLL1>, 466 <&cgu JZ4770_CLK_PLL1>, 467 <&cgu JZ4770_CLK_PLL1>, [all …]
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/linux/arch/arm/boot/dts/ |
A D | lpc18xx.dtsi | 16 #include "dt-bindings/clock/lpc18xx-cgu.h" 232 cgu: clock-controller@40050000 { label 233 compatible = "nxp,lpc1850-cgu"; 243 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>, 244 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>, 245 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>, 246 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>; 257 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>, 258 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>, 259 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>, [all …]
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/linux/Documentation/devicetree/bindings/mips/lantiq/ |
A D | lantiq,cgu.yaml | 4 $id: http://devicetree.org/schemas/mips/lantiq/lantiq,cgu.yaml# 16 - lantiq,cgu-xway 29 cgu@103000 { 30 compatible = "lantiq,cgu-xway";
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/linux/Documentation/devicetree/bindings/sound/ |
A D | ingenic,aic.yaml | 74 #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 84 clocks = <&cgu JZ4740_CLK_AIC>, 85 <&cgu JZ4740_CLK_I2S>, 86 <&cgu JZ4740_CLK_EXT>, 87 <&cgu JZ4740_CLK_PLL_HALF>;
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/linux/Documentation/devicetree/bindings/display/ |
A D | ingenic,lcd.yaml | 91 #include <dt-bindings/clock/ingenic,jz4740-cgu.h> 99 clocks = <&cgu JZ4740_CLK_LCD_PCLK>, <&cgu JZ4740_CLK_LCD>; 110 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h> 118 clocks = <&cgu JZ4725B_CLK_LCD>;
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/linux/Documentation/devicetree/bindings/mips/ingenic/ |
A D | ingenic,cpu.yaml | 47 #include <dt-bindings/clock/ingenic,jz4780-cgu.h> 58 clocks = <&cgu JZ4780_CLK_CPU>; 66 clocks = <&cgu JZ4780_CLK_CORE1>;
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/linux/Documentation/devicetree/bindings/remoteproc/ |
A D | ingenic,vpu.yaml | 61 #include <dt-bindings/clock/ingenic,jz4770-cgu.h> 72 clocks = <&cgu JZ4770_CLK_AUX>, <&cgu JZ4770_CLK_VPU>;
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