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Searched refs:clk1 (Results 1 – 25 of 33) sorted by relevance

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/linux/drivers/clk/spear/
A Dspear1340_clock.c445 struct clk *clk, *clk1; in spear1340_clk_init() local
478 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear1340_clk_init()
480 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear1340_clk_init()
491 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear1340_clk_init()
502 clk_register_clkdev(clk1, "pll3_clk", NULL); in spear1340_clk_init()
508 clk_register_clkdev(clk1, "pll4_clk", NULL); in spear1340_clk_init()
681 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1340_clk_init()
693 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1340_clk_init()
719 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); in spear1340_clk_init()
782 &clk1); in spear1340_clk_init()
[all …]
A Dspear3xx_clock.c392 struct clk *clk, *clk1, *ras_apb_clk; in spear3xx_clk_init() local
416 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear3xx_clk_init()
418 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear3xx_clk_init()
422 ARRAY_SIZE(pll_rtbl), &_lock, &clk1, NULL); in spear3xx_clk_init()
424 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear3xx_clk_init()
438 &_lock, &clk1); in spear3xx_clk_init()
456 &_lock, &clk1); in spear3xx_clk_init()
508 &_lock, &clk1); in spear3xx_clk_init()
514 &_lock, &clk1); in spear3xx_clk_init()
526 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear3xx_clk_init()
[all …]
A Dspear6xx_clock.c118 struct clk *clk, *clk1; in spear6xx_clk_init() local
138 &_lock, &clk1, NULL); in spear6xx_clk_init()
140 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear6xx_clk_init()
144 &_lock, &clk1, NULL); in spear6xx_clk_init()
146 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear6xx_clk_init()
164 &_lock, &clk1); in spear6xx_clk_init()
166 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); in spear6xx_clk_init()
184 &_lock, &clk1); in spear6xx_clk_init()
186 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); in spear6xx_clk_init()
200 &_lock, &clk1); in spear6xx_clk_init()
[all …]
A Dspear1310_clock.c388 struct clk *clk, *clk1; in spear1310_clk_init() local
423 clk_register_clkdev(clk1, "pll1_clk", NULL); in spear1310_clk_init()
434 clk_register_clkdev(clk1, "pll2_clk", NULL); in spear1310_clk_init()
445 clk_register_clkdev(clk1, "pll3_clk", NULL); in spear1310_clk_init()
451 clk_register_clkdev(clk1, "pll4_clk", NULL); in spear1310_clk_init()
556 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1310_clk_init()
585 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1310_clk_init()
597 ARRAY_SIZE(aux_rtbl), &_lock, &clk1); in spear1310_clk_init()
623 ARRAY_SIZE(gmac_rtbl), &_lock, &clk1); in spear1310_clk_init()
685 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); in spear1310_clk_init()
[all …]
/linux/drivers/clk/ti/
A Dclk-33xx.c280 struct clk *clk1, *clk2; in am33xx_dt_clk_init() local
303 clk1 = clk_get_sys(NULL, "sys_clkin_ck"); in am33xx_dt_clk_init()
305 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
308 clk_set_parent(clk2, clk1); in am33xx_dt_clk_init()
316 clk1 = clk_get_sys(NULL, "wdt1_fck"); in am33xx_dt_clk_init()
318 clk_set_parent(clk1, clk2); in am33xx_dt_clk_init()
A Dclk-43xx.c283 struct clk *clk1, *clk2; in am43xx_dt_clk_init() local
307 clk1 = clk_get_sys(NULL, "cpsw_cpts_rft_clk"); in am43xx_dt_clk_init()
309 clk_set_parent(clk1, clk2); in am43xx_dt_clk_init()
A Dadpll.c274 struct clk *clk1, in ti_adpll_init_mux() argument
286 parents[1] = __clk_get_name(clk1); in ti_adpll_init_mux()
583 struct clk *clk1) in ti_adpll_init_clkout() argument
614 parent_names[1] = __clk_get_name(clk1); in ti_adpll_init_clkout()
/linux/drivers/clocksource/
A Dtimer-sp804.c259 struct clk *clk1, *clk2; in sp804_of_init() local
278 clk1 = of_clk_get(np, 0); in sp804_of_init()
279 if (IS_ERR(clk1)) in sp804_of_init()
280 clk1 = NULL; in sp804_of_init()
291 clk2 = clk1; in sp804_of_init()
307 name, clk1, 1); in sp804_of_init()
312 ret = sp804_clockevents_init(timer1_base, irq, clk1, name); in sp804_of_init()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dgf100.c279 u32 clk0, clk1 = 0; in calc_clk() local
292 clk1 = calc_pll(clk, idx, freq, &info->coef); in calc_clk()
294 clk1 = cstate->domain[nv_clk_src_hubk06]; in calc_clk()
295 clk1 = calc_div(clk, idx, clk1, freq, &div1P); in calc_clk()
299 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { in calc_clk()
318 info->freq = clk1; in calc_clk()
A Dgk104.c293 u32 clk0, clk1 = 0; in calc_clk() local
306 clk1 = calc_pll(clk, idx, freq, &info->coef); in calc_clk()
308 clk1 = cstate->domain[nv_clk_src_hubk06]; in calc_clk()
309 clk1 = calc_div(clk, idx, clk1, freq, &div1P); in calc_clk()
313 if (abs((int)freq - clk0) <= abs((int)freq - clk1)) { in calc_clk()
332 info->freq = clk1; in calc_clk()
A Dmcp77.c184 u32 clk0 = src, clk1 = src; in calc_P() local
187 clk1 = clk0 << (*div ? 1 : 0); in calc_P()
193 if (target - clk0 <= clk1 - target) in calc_P()
196 return clk1; in calc_P()
A Dnv50.c347 u32 clk0 = src, clk1 = src; in calc_div() local
350 clk1 = clk0 << (*div ? 1 : 0); in calc_div()
356 if (target - clk0 <= clk1 - target) in calc_div()
359 return clk1; in calc_div()
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/
A Dusb.txt12 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
16 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
A Ducc.txt25 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
29 "clk1" through "clk24": clock source is CLK1-CLK24, respectively
/linux/Documentation/devicetree/bindings/sound/
A Dqcom,lpass-cpu.yaml132 - const: mi2s-bit-clk1
154 - const: mi2s-bit-clk1
204 "mi2s-bit-clk0", "mi2s-bit-clk1";
/linux/drivers/clk/rockchip/
A Dclk-rk3188.c815 struct clk *clk1, *clk2; in rk3188a_clk_init() local
834 clk1 = __clk_lookup("aclk_cpu_pre"); in rk3188a_clk_init()
836 if (clk1 && clk2) { in rk3188a_clk_init()
837 rate = clk_get_rate(clk1); in rk3188a_clk_init()
839 ret = clk_set_parent(clk1, clk2); in rk3188a_clk_init()
844 clk_set_rate(clk1, rate); in rk3188a_clk_init()
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
A Duqe_serial.txt8 should be "clk1"-"clk28" for external clock source.
A Dnetwork.txt56 Must be "clk1"-"clk24" for external clock source.
/linux/drivers/clk/zynq/
A Dclkc.c174 enum zynq_clk clk1, const char *clk_name0, in zynq_clk_register_periph_clk() argument
199 clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, in zynq_clk_register_periph_clk()
210 clks[clk1] = ERR_PTR(-ENOMEM); in zynq_clk_register_periph_clk()
/linux/Documentation/devicetree/bindings/arm/tegra/
A Dnvidia,tegra186-pmc.txt59 pex-clk-bias pex-clk3 pex-clk2 pex-clk1
A Dnvidia,tegra20-pmc.yaml261 hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
267 hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
/linux/arch/arm/boot/dts/
A Dlpc4350-hitex-eval.dts230 pins = "clk0", "clk1", "clk2", "clk3";
A Dtegra30-colibri.dtsi29 clk1-out-pw4 {
603 clk1-req-pee2 {
A Dlpc4357-ea4357-devkit.dts260 pins = "clk0", "clk1", "clk2", "clk3";
A Dtegra30-apalis-v1.1.dtsi63 clk1-out-pw4 {
146 clk1-req-pee2 {

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