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Searched refs:clk_mask (Results 1 – 21 of 21) sorted by relevance

/linux/drivers/clk/sunxi/
A Dclk-usb.c83 u32 clk_mask; member
110 qty = find_last_bit((unsigned long *)&data->clk_mask, in sunxi_usb_clk_setup()
123 for_each_set_bit(i, (unsigned long *)&data->clk_mask, in sunxi_usb_clk_setup()
166 .clk_mask = BIT(8) | BIT(7) | BIT(6),
179 .clk_mask = BIT(8) | BIT(6),
190 .clk_mask = BIT(18) | BIT(17) | BIT(16) | BIT(10) | BIT(9) | BIT(8),
201 .clk_mask = BIT(16) | BIT(11) | BIT(10) | BIT(9) | BIT(8),
212 .clk_mask = BIT(19) | BIT(18) | BIT(17) | BIT(16) |
224 .clk_mask = BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
238 .clk_mask = BIT(10) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1),
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dnv50.c447 clk_mask(hwsq, mast, mastm, 0x00000000); in nv50_clk_calc()
448 clk_mask(hwsq, divs, divsm, divsv); in nv50_clk_calc()
449 clk_mask(hwsq, mast, mastm, mastv); in nv50_clk_calc()
455 clk_mask(hwsq, mast, 0x001000b0, 0x00100080); in nv50_clk_calc()
457 clk_mask(hwsq, mast, 0x000000b3, 0x00000081); in nv50_clk_calc()
464 clk_mask(hwsq, nvpll[0], 0xc03f0100, in nv50_clk_calc()
466 clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
476 clk_mask(hwsq, mast, 0x00100033, 0x00000023); in nv50_clk_calc()
482 clk_mask(hwsq, spll[0], 0xc03f0100, in nv50_clk_calc()
484 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M); in nv50_clk_calc()
[all …]
A Dseq.h11 #define clk_mask(s,r,m,d) hwsq_mask(&(s)->base, &(s)->r_##r, (m), (d)) macro
/linux/drivers/soc/imx/
A Dimx8m-blk-ctrl.c39 u32 clk_mask; member
100 regmap_set_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); in imx8m_blk_ctrl_power_on()
141 regmap_clear_bits(bc->regmap, BLK_CLK_EN, data->clk_mask); in imx8m_blk_ctrl_power_off()
424 .clk_mask = BIT(1),
432 .clk_mask = BIT(0),
440 .clk_mask = BIT(2),
484 .clk_mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
491 .clk_mask = BIT(6) | BIT(7),
499 .clk_mask = BIT(8) | BIT(9),
508 .clk_mask = BIT(10) | BIT(11),
/linux/drivers/gpu/drm/msm/edp/
A Dedp_ctrl.c195 DBG("mask=%x", clk_mask); in edp_clk_enable()
197 if (clk_mask & EDP_CLK_MASK_AHB) { in edp_clk_enable()
204 if (clk_mask & EDP_CLK_MASK_AUX) { in edp_clk_enable()
262 if (clk_mask & EDP_CLK_MASK_PIXEL) in edp_clk_enable()
265 if (clk_mask & EDP_CLK_MASK_LINK) in edp_clk_enable()
268 if (clk_mask & EDP_CLK_MASK_AUX) in edp_clk_enable()
271 if (clk_mask & EDP_CLK_MASK_AHB) in edp_clk_enable()
281 if (clk_mask & EDP_CLK_MASK_PIXEL) in edp_clk_disable()
283 if (clk_mask & EDP_CLK_MASK_LINK) in edp_clk_disable()
285 if (clk_mask & EDP_CLK_MASK_AUX) in edp_clk_disable()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_clk_mgr.c814 const struct clk_mgr_mask *clk_mask) in dce_clk_mgr_construct() argument
824 clk_mgr_dce->clk_mgr_mask = clk_mask; in dce_clk_mgr_construct()
847 const struct clk_mgr_mask *clk_mask) in dce_clk_mgr_create() argument
861 clk_mgr_dce, ctx, regs, clk_shift, clk_mask); in dce_clk_mgr_create()
870 const struct clk_mgr_mask *clk_mask) in dce110_clk_mgr_create() argument
884 clk_mgr_dce, ctx, regs, clk_shift, clk_mask); in dce110_clk_mgr_create()
895 const struct clk_mgr_mask *clk_mask) in dce112_clk_mgr_create() argument
909 clk_mgr_dce, ctx, regs, clk_shift, clk_mask); in dce112_clk_mgr_create()
/linux/sound/pci/ice1712/
A Drevo.c237 .clk_mask = VT1724_REVO_CCLK,
259 .clk_mask = VT1724_REVO_CCLK,
280 .clk_mask = VT1724_REVO_CCLK,
298 .clk_mask = VT1724_REVO_CCLK,
348 .clk_mask = VT1724_REVO_CCLK,
A Ddelta.c447 .clk_mask = ICE1712_DELTA_AP_CCLK,
468 .clk_mask = ICE1712_DELTA_AP_CCLK,
490 .clk_mask = ICE1712_DELTA_1010LT_CCLK,
512 .clk_mask = ICE1712_DELTA_66E_CCLK,
535 .clk_mask = ICE1712_DELTA_CODEC_SERIAL_CLOCK,
557 .clk_mask = ICE1712_VX442_CCLK,
A Dak4xxx.c77 tmp &= ~priv->clk_mask; in snd_ice1712_akm4xxx_write()
88 tmp |= priv->clk_mask; in snd_ice1712_akm4xxx_write()
A Dews.c347 .clk_mask = ICE1712_EWS88_SERIAL_CLOCK,
368 .clk_mask = ICE1712_EWS88_SERIAL_CLOCK,
389 .clk_mask = ICE1712_6FIRE_SERIAL_CLOCK,
A Dhoontech.c291 .clk_mask = ICE1712_STDSP24_SERIAL_CLOCK, in snd_ice1712_value_init()
A Dice1712.h255 unsigned int clk_mask; /* CLK gpio bit */ member
A Dphase.c101 .clk_mask = 1 << 5,
/linux/arch/ia64/kernel/
A Dfsyscall_gtod_data.h19 u64 clk_mask; member
A Dtime.c437 fsyscall_gtod_data.clk_mask = tk->tkr_mono.mask; in update_vsyscall()
A Dasm-offsets.c275 offsetof (struct fsyscall_gtod_data_t, clk_mask)); in foo()
/linux/include/linux/
A Dfs_enet_pd.h128 u32 clk_mask; member
/linux/drivers/spi/
A Dspi-ti-qspi.c145 u32 clk_ctrl_reg, clk_rate, clk_mask; in ti_qspi_setup() local
190 clk_mask = QSPI_CLK_EN | clk_div; in ti_qspi_setup()
191 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); in ti_qspi_setup()
192 ctx_reg->clkctrl = clk_mask; in ti_qspi_setup()
/linux/drivers/gpu/drm/radeon/
A Dradeon_combios.c416 u32 clk_mask, in combios_setup_i2c_bus() argument
520 if (clk_mask && data_mask) { in combios_setup_i2c_bus()
522 i2c.mask_clk_mask = clk_mask; in combios_setup_i2c_bus()
524 i2c.a_clk_mask = clk_mask; in combios_setup_i2c_bus()
526 i2c.en_clk_mask = clk_mask; in combios_setup_i2c_bus()
528 i2c.y_clk_mask = clk_mask; in combios_setup_i2c_bus()
/linux/drivers/gpu/drm/amd/pm/swsmu/
A Damdgpu_smu.c395 smu->user_dpm_profile.clk_mask[clk_type]) { in smu_restore_dpm_user_profile()
397 smu->user_dpm_profile.clk_mask[clk_type]); in smu_restore_dpm_user_profile()
1910 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask)); in smu_force_performance_level()
1952 smu->user_dpm_profile.clk_mask[clk_type] = mask; in smu_force_smuclk_levels()
/linux/drivers/gpu/drm/amd/pm/inc/
A Damdgpu_smu.h240 uint32_t clk_mask[SMU_CLK_COUNT]; member

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