/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
A D | clk_mgr.c | 115 void clk_mgr_optimize_pwr_state(const struct dc *dc, struct clk_mgr *clk_mgr) in clk_mgr_optimize_pwr_state() argument 145 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local 158 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local 168 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local 178 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local 202 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local 216 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local 244 struct clk_mgr_internal *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local 271 struct clk_mgr_vgh *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local 282 struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL); in dc_clk_mgr_create() local [all …]
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A D | Makefile | 26 CLK_MGR = clk_mgr.o 28 AMD_DAL_CLK_MGR = $(addprefix $(AMDDALPATH)/dc/clk_mgr/,$(CLK_MGR)) 39 AMD_DAL_CLK_MGR_DCE60 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce60/,$(CLK_MGR_DCE60)) 49 AMD_DAL_CLK_MGR_DCE100 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce100/,$(CLK_MGR_DCE100)) 58 AMD_DAL_CLK_MGR_DCE110 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce110/,$(CLK_MGR_DCE110)) 66 AMD_DAL_CLK_MGR_DCE112 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dce112/,$(CLK_MGR_DCE112)) 83 AMD_DAL_CLK_MGR_DCN10 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn10/,$(CLK_MGR_DCN10)) 92 AMD_DAL_CLK_MGR_DCN20 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn20/,$(CLK_MGR_DCN20)) 116 AMD_DAL_CLK_MGR_DCN21 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn21/,$(CLK_MGR_DCN21)) 130 AMD_DAL_CLK_MGR_DCN30 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn30/,$(CLK_MGR_DCN30)) [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
A D | dcn30_clk_mgr.c | 55 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 58 (clk_mgr->regs->reg) 176 if (!clk_mgr->smu_present) in dcn3_init_clocks() 386 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32); in dcn3_notify_wm_ranges() 387 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF); in dcn3_notify_wm_ranges() 515 static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr) in dcn3_init_clocks_fpga() argument 535 clk_mgr->base.ctx = ctx; in dcn3_clk_mgr_construct() 541 clk_mgr->dccg = dccg; in dcn3_clk_mgr_construct() 559 clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr); in dcn3_clk_mgr_construct() 579 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL); in dcn3_clk_mgr_construct() [all …]
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A D | dcn30_clk_mgr_smu_msg.c | 171 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_dram_addr_high() 179 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_dram_addr_low() 187 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_transfer_wm_table_smu_2_dram() 195 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_transfer_wm_table_dram_2_smu() 209 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_hard_min_by_freq() 227 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_hard_max_by_freq() 258 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_get_dpm_freq_by_index() 276 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_get_dc_mode_max_dpm_freq() 288 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_min_deep_sleep_dcef_clk() 296 dcn30_smu_send_msg_with_param(clk_mgr, in dcn30_smu_set_num_of_displays() [all …]
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A D | dcn30_clk_mgr_smu_msg.h | 92 bool dcn30_smu_test_message(struct clk_mgr_internal *clk_mgr, uint32_t input); 93 bool dcn30_smu_get_smu_version(struct clk_mgr_internal *clk_mgr, unsigned int *version); 94 bool dcn30_smu_check_driver_if_version(struct clk_mgr_internal *clk_mgr); 95 bool dcn30_smu_check_msg_header_version(struct clk_mgr_internal *clk_mgr); 96 void dcn30_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); 97 void dcn30_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); 98 void dcn30_smu_transfer_wm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); 99 void dcn30_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); 103 unsigned int dcn30_smu_get_dc_mode_max_dpm_freq(struct clk_mgr_internal *clk_mgr, PPCLK_e clk); 105 void dcn30_smu_set_num_of_displays(struct clk_mgr_internal *clk_mgr, uint32_t num_displays); [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
A D | dcn31_smu.c | 133 clk_mgr, in dcn31_smu_get_smu_version() 148 clk_mgr, in dcn31_smu_set_dispclk() 163 clk_mgr, in dcn31_smu_set_dprefclk() 183 clk_mgr, in dcn31_smu_set_hard_min_dcfclk() 201 clk_mgr, in dcn31_smu_set_min_deep_sleep_dcfclk() 216 clk_mgr, in dcn31_smu_set_dppclk() 233 clk_mgr, in dcn31_smu_set_display_idle_optimization() 251 clk_mgr, in dcn31_smu_enable_phy_refclk_pwrdwn() 262 clk_mgr, in dcn31_smu_enable_pme_wa() 317 clk_mgr, in dcn31_smu_set_Z9_support() [all …]
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A D | dcn31_clk_mgr.c | 288 static void dcn31_init_clocks(struct clk_mgr *clk_mgr) in dcn31_init_clocks() argument 471 if (!clk_mgr->smu_ver) in dcn31_notify_wm_ranges() 493 if (!clk_mgr->smu_ver) in dcn31_get_dpm_table_from_smu() 642 clk_mgr->base.dccg = dccg; in dcn31_clk_mgr_construct() 651 clk_mgr->base.base.ctx, in dcn31_clk_mgr_construct() 663 clk_mgr->base.base.ctx, in dcn31_clk_mgr_construct() 680 clk_mgr->base.smu_ver = dcn31_smu_get_smu_version(&clk_mgr->base); in dcn31_clk_mgr_construct() 682 if (clk_mgr->base.smu_ver) in dcn31_clk_mgr_construct() 686 clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base); in dcn31_clk_mgr_construct() 709 &clk_mgr->base, in dcn31_clk_mgr_construct() [all …]
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A D | dcn31_smu.h | 254 int dcn31_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); 255 int dcn31_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 256 int dcn31_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); 259 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); 261 void dcn31_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); 262 void dcn31_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); 264 void dcn31_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); 265 void dcn31_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); 266 void dcn31_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr); 268 void dcn31_smu_set_Z9_support(struct clk_mgr_internal *clk_mgr, bool support); [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
A D | dcn20_clk_mgr.c | 45 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 48 (clk_mgr->regs->reg) 110 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto() 344 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, in dcn2_update_clocks_fpga() argument 391 if (clk_mgr->clks.fclk_khz > clk_mgr->clks.dppclk_khz) in dcn2_update_clocks_fpga() 392 clk_mgr->clks.dppclk_khz = clk_mgr->clks.fclk_khz; in dcn2_update_clocks_fpga() 393 if (clk_mgr->clks.dppclk_khz > clk_mgr->clks.fclk_khz) in dcn2_update_clocks_fpga() 394 clk_mgr->clks.fclk_khz = clk_mgr->clks.dppclk_khz; in dcn2_update_clocks_fpga() 401 dm_set_dcn_clocks(clk_mgr->ctx, &clk_mgr->clks); in dcn2_update_clocks_fpga() 404 void dcn2_init_clocks(struct clk_mgr *clk_mgr) in dcn2_init_clocks() argument [all …]
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A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg, 33 void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr, 36 void dcn20_update_clocks_update_dpp_dto(struct clk_mgr_internal *clk_mgr, 39 void dcn2_init_clocks(struct clk_mgr *clk_mgr); 42 struct clk_mgr_internal *clk_mgr, 48 void dcn2_get_clock(struct clk_mgr *clk_mgr, 53 void dcn20_update_clocks_update_dentist(struct clk_mgr_internal *clk_mgr, 56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
A D | dcn201_clk_mgr.c | 43 (clk_mgr->regs->reg) 58 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 61 clk_mgr->base.ctx 63 clk_mgr->base.ctx->logger 77 void dcn201_update_clocks_vbios(struct clk_mgr *clk_mgr, in dcn201_update_clocks_vbios() argument 113 static void dcn201_init_clocks(struct clk_mgr *clk_mgr) in dcn201_init_clocks() argument 221 clk_mgr->base.ctx = ctx; in dcn201_clk_mgr_construct() 223 clk_mgr->regs = &clk_mgr_regs; in dcn201_clk_mgr_construct() 227 clk_mgr->dccg = dccg; in dcn201_clk_mgr_construct() 233 clk_mgr->ss_on_dprefclk = false; in dcn201_clk_mgr_construct() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
A D | rv1_clk_mgr.c | 37 void rv1_init_clocks(struct clk_mgr *clk_mgr) in rv1_init_clocks() argument 47 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz; in rv1_determine_dppclk_threshold() 89 struct clk_mgr_internal *clk_mgr, in ramp_up_dispclk_with_dpp() argument 161 clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold); in ramp_up_dispclk_with_dpp() 162 clk_mgr->funcs->set_dprefclk(clk_mgr); in ramp_up_dispclk_with_dpp() 180 clk_mgr->funcs->set_dispclk(clk_mgr, new_clocks->dispclk_khz); in ramp_up_dispclk_with_dpp() 181 clk_mgr->funcs->set_dprefclk(clk_mgr); in ramp_up_dispclk_with_dpp() 205 ASSERT(clk_mgr->pp_smu); in rv1_update_clocks() 299 if (clk_mgr->pp_smu) { in rv1_enable_pme_wa() 324 clk_mgr->base.ctx = ctx; in rv1_clk_mgr_construct() [all …]
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A D | rv1_clk_mgr_vbios_smu.c | 84 static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, … in rv1_smu_wait_for_response() argument 102 int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr, unsigned int msg_id, unsign… in rv1_vbios_smu_send_msg_with_param() argument 115 result = rv1_smu_wait_for_response(clk_mgr, 10, 1000); in rv1_vbios_smu_send_msg_with_param() 123 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz) in rv1_vbios_smu_set_dispclk() argument 126 struct dc *dc = clk_mgr->base.ctx->dc; in rv1_vbios_smu_set_dispclk() 131 clk_mgr, in rv1_vbios_smu_set_dispclk() 137 if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz) in rv1_vbios_smu_set_dispclk() 146 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr) in rv1_vbios_smu_set_dprefclk() argument 151 clk_mgr, in rv1_vbios_smu_set_dprefclk() 153 khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz)); in rv1_vbios_smu_set_dprefclk()
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
A D | clk_mgr.h | 232 void (*update_clocks)(struct clk_mgr *clk_mgr, 236 int (*get_dp_ref_clk_frequency)(struct clk_mgr *clk_mgr); 238 void (*set_low_power_state)(struct clk_mgr *clk_mgr); 240 void (*init_clocks)(struct clk_mgr *clk_mgr); 242 void (*enable_pme_wa) (struct clk_mgr *clk_mgr); 243 void (*get_clock)(struct clk_mgr *clk_mgr, 250 void (*notify_wm_ranges)(struct clk_mgr *clk_mgr); 262 void (*set_hard_max_memclk)(struct clk_mgr *clk_mgr); 265 void (*get_memclk_states_from_smu)(struct clk_mgr *clk_mgr); 268 bool (*is_smu_present)(struct clk_mgr *clk_mgr); [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
A D | rn_clk_mgr_vbios_smu.c | 113 clk_mgr, in rn_vbios_smu_get_smu_version() 127 clk_mgr, in rn_vbios_smu_set_dispclk() 151 clk_mgr, in rn_vbios_smu_set_dprefclk() 168 clk_mgr, in rn_vbios_smu_set_hard_min_dcfclk() 183 clk_mgr, in rn_vbios_smu_set_min_deep_sleep_dcfclk() 193 clk_mgr, in rn_vbios_smu_set_phyclk() 204 clk_mgr, in rn_vbios_smu_set_dppclk() 224 clk_mgr, in rn_vbios_smu_set_dcn_low_power_state() 232 clk_mgr, in rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn() 240 clk_mgr, in rn_vbios_smu_enable_pme_wa() [all …]
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A D | rn_clk_mgr.c | 218 clk_mgr, in rn_update_clocks() 228 clk_mgr, in rn_update_clocks() 241 clk_mgr, in rn_update_clocks() 458 void rn_init_clocks(struct clk_mgr *clk_mgr) in rn_init_clocks() argument 950 clk_mgr->base.ctx = ctx; in rn_clk_mgr_construct() 953 clk_mgr->pp_smu = pp_smu; in rn_clk_mgr_construct() 955 clk_mgr->dccg = dccg; in rn_clk_mgr_construct() 960 clk_mgr->ss_on_dprefclk = false; in rn_clk_mgr_construct() 963 clk_mgr->smu_ver = rn_vbios_smu_get_smu_version(clk_mgr); in rn_clk_mgr_construct() 979 clk_mgr->base.dentist_vco_freq_khz = get_vco_frequency_from_reg(clk_mgr); in rn_clk_mgr_construct() [all …]
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A D | rn_clk_mgr_vbios_smu.h | 29 int rn_vbios_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); 30 int rn_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 31 int rn_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); 32 int rn_vbios_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); 33 int rn_vbios_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_d… 34 void rn_vbios_smu_set_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz); 35 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); 36 void rn_vbios_smu_set_dcn_low_power_state(struct clk_mgr_internal *clk_mgr, int display_count); 37 void rn_vbios_smu_enable_48mhz_tmdp_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); 38 void rn_vbios_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
A D | dcn301_smu.c | 92 struct clk_mgr_internal *clk_mgr, in dcn301_smu_send_msg_with_param() argument 134 clk_mgr, in dcn301_smu_set_dispclk() 148 clk_mgr, in dcn301_smu_set_dprefclk() 164 clk_mgr, in dcn301_smu_set_hard_min_dcfclk() 178 clk_mgr, in dcn301_smu_set_min_deep_sleep_dcfclk() 192 clk_mgr, in dcn301_smu_set_dppclk() 206 clk_mgr, in dcn301_smu_set_display_idle_optimization() 223 clk_mgr, in dcn301_smu_enable_phy_refclk_pwrdwn() 231 clk_mgr, in dcn301_smu_enable_pme_wa() 240 dcn301_smu_send_msg_with_param(clk_mgr, in dcn301_smu_set_dram_addr_high() [all …]
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A D | vg_clk_mgr.c | 52 #define TO_CLK_MGR_VGH(clk_mgr)\ argument 389 void vg_init_clocks(struct clk_mgr *clk_mgr) in vg_init_clocks() argument 460 if (!clk_mgr->smu_ver) in vg_notify_wm_ranges() 714 if (!clk_mgr->smu_ver) in vg_get_dpm_table_from_smu() 742 clk_mgr->base.dccg = dccg; in vg_clk_mgr_construct() 751 clk_mgr->base.base.ctx, in vg_clk_mgr_construct() 763 clk_mgr->base.base.ctx, in vg_clk_mgr_construct() 781 clk_mgr->base.smu_ver = dcn301_smu_get_smu_version(&clk_mgr->base); in vg_clk_mgr_construct() 783 if (clk_mgr->base.smu_ver) in vg_clk_mgr_construct() 810 &clk_mgr->base, in vg_clk_mgr_construct() [all …]
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A D | dcn301_smu.h | 150 int dcn301_smu_get_smu_version(struct clk_mgr_internal *clk_mgr); 151 int dcn301_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz); 152 int dcn301_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr); 153 int dcn301_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz); 155 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz); 157 void dcn301_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable); 158 void dcn301_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr); 159 void dcn301_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high); 160 void dcn301_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low); 161 void dcn301_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr); [all …]
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/linux/drivers/gpu/drm/amd/display/dc/dce/ |
A D | dce_clk_mgr.c | 48 clk_mgr->ctx->logger 148 static int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) in dce_get_dp_ref_freq_khz() argument 174 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr) in dce12_get_dp_ref_freq_khz() argument 214 struct clk_mgr *clk_mgr, in dce_get_required_clocks_state() argument 247 struct clk_mgr *clk_mgr, in dce_set_clock() argument 466 void dce121_clock_patch_xgmi_ss_info(struct clk_mgr *clk_mgr) in dce121_clock_patch_xgmi_ss_info() argument 670 static void dce_update_clocks(struct clk_mgr *clk_mgr, in dce_update_clocks() argument 697 static void dce11_update_clocks(struct clk_mgr *clk_mgr, in dce11_update_clocks() argument 724 static void dce112_update_clocks(struct clk_mgr *clk_mgr, in dce112_update_clocks() argument 751 static void dce12_update_clocks(struct clk_mgr *clk_mgr, in dce12_update_clocks() argument [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/ |
A D | dce60_clk_mgr.c | 47 (clk_mgr->regs->reg) 51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 101 * clk_mgr->base.dentist_vco_freq_khz) / target_div; in dce60_get_dp_ref_freq_khz() 120 static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, in dce60_update_clocks() 161 struct clk_mgr_internal *clk_mgr) in dce60_clk_mgr_construct() argument 163 dce_clk_mgr_construct(ctx, clk_mgr); in dce60_clk_mgr_construct() 165 memcpy(clk_mgr->max_clks_by_state, in dce60_clk_mgr_construct() 169 clk_mgr->regs = &disp_clk_regs; in dce60_clk_mgr_construct() 170 clk_mgr->clk_mgr_shift = &disp_clk_shift; in dce60_clk_mgr_construct() 171 clk_mgr->clk_mgr_mask = &disp_clk_mask; in dce60_clk_mgr_construct() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
A D | dce112_clk_mgr.c | 129 struct dc_bios *bp = clk_mgr->base.ctx->dc_bios; in dce112_set_dispclk() 130 struct dc *dc = clk_mgr->base.ctx->dc; in dce112_set_dispclk() 139 clk_mgr->base.dentist_vco_freq_khz / 62); in dce112_set_dispclk() 164 clk_mgr->dfs_bypass_disp_clk = actual_clock; in dce112_set_dispclk() 229 struct clk_mgr_internal *clk_mgr) in dce112_clk_mgr_construct() argument 231 dce_clk_mgr_construct(ctx, clk_mgr); in dce112_clk_mgr_construct() 233 memcpy(clk_mgr->max_clks_by_state, in dce112_clk_mgr_construct() 237 clk_mgr->regs = &disp_clk_regs; in dce112_clk_mgr_construct() 238 clk_mgr->clk_mgr_shift = &disp_clk_shift; in dce112_clk_mgr_construct() 239 clk_mgr->clk_mgr_mask = &disp_clk_mask; in dce112_clk_mgr_construct() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
A D | dce_clk_mgr.c | 47 (clk_mgr->regs->reg) 51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name 195 struct clk_mgr *clk_mgr_base, in dce_get_required_clocks_state() 230 struct clk_mgr *clk_mgr_base, in dce_set_clock() 436 struct clk_mgr_internal *clk_mgr) in dce_clk_mgr_construct() argument 438 struct clk_mgr *base = &clk_mgr->base; in dce_clk_mgr_construct() 441 memcpy(clk_mgr->max_clks_by_state, in dce_clk_mgr_construct() 448 clk_mgr->regs = &disp_clk_regs; in dce_clk_mgr_construct() 451 clk_mgr->dfs_bypass_disp_clk = 0; in dce_clk_mgr_construct() 455 clk_mgr->ss_on_dprefclk = false; in dce_clk_mgr_construct() [all …]
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
A D | dce120_clk_mgr.c | 84 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce12_update_clocks() 128 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) in dce120_clk_mgr_construct() argument 130 dce_clk_mgr_construct(ctx, clk_mgr); in dce120_clk_mgr_construct() 132 memcpy(clk_mgr->max_clks_by_state, in dce120_clk_mgr_construct() 136 clk_mgr->base.dprefclk_khz = 600000; in dce120_clk_mgr_construct() 137 clk_mgr->base.funcs = &dce120_funcs; in dce120_clk_mgr_construct() 140 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr) in dce121_clk_mgr_construct() argument 142 dce120_clk_mgr_construct(ctx, clk_mgr); in dce121_clk_mgr_construct() 143 clk_mgr->base.dprefclk_khz = 625000; in dce121_clk_mgr_construct() 150 dce121_clock_patch_xgmi_ss_info(clk_mgr); in dce121_clk_mgr_construct()
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