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Searched refs:clk_mgr_base (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c170 if (!clk_mgr_base->bw_params) in dcn3_init_clocks()
215 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base); in dcn3_init_clocks()
249 struct dc *dc = clk_mgr_base->ctx->dc; in dcn3_update_clocks()
264 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn3_update_clocks()
269 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn3_update_clocks()
299 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn3_update_clocks()
308 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_update_clocks()
356 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in dcn3_update_clocks()
400 if (clk_mgr_base->clks.p_state_change_support) in dcn3_set_hard_min_memclk()
405 …clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].mem… in dcn3_set_hard_min_memclk()
[all …]
A Ddcn30_clk_mgr.h29 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
A Ddcn201_clk_mgr.c122 static void dcn201_update_clocks(struct clk_mgr *clk_mgr_base, in dcn201_update_clocks() argument
128 struct dc *dc = clk_mgr_base->ctx->dc; in dcn201_update_clocks()
141 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks()
145 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn201_update_clocks()
154 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in dcn201_update_clocks()
161 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn201_update_clocks()
168 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn201_update_clocks()
173 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn201_update_clocks()
174 clk_mgr_base->clks.p_state_change_support = p_state_change_support; in dcn201_update_clocks()
178 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz; in dcn201_update_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
A Drn_clk_mgr.c125 void rn_update_clocks(struct clk_mgr *clk_mgr_base, in rn_update_clocks() argument
131 struct dc *dc = clk_mgr_base->ctx->dc; in rn_update_clocks()
210 …clk_mgr_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispc… in rn_update_clocks()
220 clk_mgr_base->clks.dppclk_khz, in rn_update_clocks()
223 clk_mgr_base->clks.actual_dppclk_khz = in rn_update_clocks()
230 clk_mgr_base->clks.actual_dppclk_khz, in rn_update_clocks()
236 clk_mgr_base->clks.actual_dppclk_khz = in rn_update_clocks()
243 clk_mgr_base->clks.actual_dppclk_khz, in rn_update_clocks()
251 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in rn_update_clocks()
531 build_watermark_ranges(clk_mgr_base->bw_params, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
A Ddcn31_clk_mgr.c104 struct dc *dc = clk_mgr_base->ctx->dc; in dcn31_disable_otg_wa()
128 struct dc *dc = clk_mgr_base->ctx->dc; in dcn31_update_clocks()
151 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn31_update_clocks()
164 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn31_update_clocks()
177 clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en; in dcn31_update_clocks()
190 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn31_update_clocks()
209 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in dcn31_update_clocks()
214 dcn31_disable_otg_wa(clk_mgr_base, true); in dcn31_update_clocks()
216 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn31_update_clocks()
218 dcn31_disable_otg_wa(clk_mgr_base, false); in dcn31_update_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
A Ddcn20_clk_mgr.c209 void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, in dcn2_update_clocks() argument
215 struct dc *dc = clk_mgr_base->ctx->dc; in dcn2_update_clocks()
232 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
237 dcn2_read_clocks_from_hw_dentist(clk_mgr_base); in dcn2_update_clocks()
264 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in dcn2_update_clocks()
277 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz; in dcn2_update_clocks()
285 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support; in dcn2_update_clocks()
340 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in dcn2_update_clocks()
412 void dcn2_enable_pme_wa(struct clk_mgr *clk_mgr_base) in dcn2_enable_pme_wa() argument
513 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) { in dcn2_notify_link_rate_change()
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A Ddcn20_clk_mgr.h56 void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
A Drv1_clk_mgr.c190 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base, in rv1_update_clocks() argument
195 struct dc *dc = clk_mgr_base->ctx->dc; in rv1_update_clocks()
227 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
228 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz in rv1_update_clocks()
229 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz in rv1_update_clocks()
230 || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz) in rv1_update_clocks()
234 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz; in rv1_update_clocks()
243 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz; in rv1_update_clocks()
249 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in rv1_update_clocks()
278 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in rv1_update_clocks()
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A Drv1_clk_mgr_clk.c52 …egisters(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base) in rv1_dump_clk_registers() argument
54 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in rv1_dump_clk_registers()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/
A Ddce112_clk_mgr.c70 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz) in dce112_set_clock() argument
72 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_set_clock()
74 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce112_set_clock()
75 struct dc *dc = clk_mgr_base->ctx->dc; in dce112_set_clock()
104 if (!((clk_mgr_base->ctx->asic_id.chip_family == FAMILY_AI) && in dce112_set_clock()
105 ASICREV_IS_VEGA20_P(clk_mgr_base->ctx->asic_id.hw_internal_rev))) in dce112_set_clock()
195 static void dce112_update_clocks(struct clk_mgr *clk_mgr_base, in dce112_update_clocks() argument
199 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce112_update_clocks()
216 patched_disp_clk = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce112_update_clocks()
217 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce112_update_clocks()
[all …]
A Ddce112_clk_mgr.h35 int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/
A Ddce120_clk_mgr.c84 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base, in dce12_update_clocks() argument
88 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_update_clocks()
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce12_update_clocks()
109 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
112 if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) { in dce12_update_clocks()
115 clk_mgr_base->clks.phyclk_khz = max_pix_clk; in dce12_update_clocks()
117 dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req); in dce12_update_clocks()
119 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce12_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/
A Ddce60_clk_mgr.c83 static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce60_get_dp_ref_freq_khz() argument
85 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_get_dp_ref_freq_khz()
120 static void dce60_update_clocks(struct clk_mgr *clk_mgr_base, in dce60_update_clocks() argument
124 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce60_update_clocks()
132 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce60_update_clocks()
136 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce60_update_clocks()
140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks()
141 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce60_update_clocks()
142 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce60_update_clocks()
144 dce60_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce60_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
A Ddce_clk_mgr.c129 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce_get_dp_ref_freq_khz() argument
131 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce_get_dp_ref_freq_khz()
155 int dce12_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base) in dce12_get_dp_ref_freq_khz() argument
157 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce12_get_dp_ref_freq_khz()
195 struct clk_mgr *clk_mgr_base, in dce_get_required_clocks_state() argument
230 struct clk_mgr *clk_mgr_base, in dce_set_clock() argument
235 struct dc_bios *bp = clk_mgr_base->ctx->dc_bios; in dce_set_clock()
395 static void dce_update_clocks(struct clk_mgr *clk_mgr_base, in dce_update_clocks() argument
416 patched_disp_clk = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce_update_clocks()
417 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce_update_clocks()
[all …]
A Ddce_clk_mgr.h34 int dce_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base);
36 struct clk_mgr *clk_mgr_base,
51 struct clk_mgr *clk_mgr_base,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
A Dvg_clk_mgr.c92 void vg_update_clocks(struct clk_mgr *clk_mgr_base, in vg_update_clocks() argument
98 struct dc *dc = clk_mgr_base->ctx->dc; in vg_update_clocks()
125 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in vg_update_clocks()
135 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in vg_update_clocks()
140 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz; in vg_update_clocks()
159 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz; in vg_update_clocks()
164 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in vg_update_clocks()
245 vg_dump_clk_registers_internal(&internal, clk_mgr_base); in vg_dump_clk_registers()
377 vg_dump_clk_registers(&sb, clk_mgr_base, &log_info); in vg_get_clk_states()
382 static void vg_enable_pme_wa(struct clk_mgr *clk_mgr_base) in vg_enable_pme_wa() argument
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/
A Ddce110_clk_mgr.c249 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, in dce11_update_clocks() argument
253 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dce11_update_clocks()
261 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); in dce11_update_clocks()
265 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) in dce11_update_clocks()
269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
271 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
273 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); in dce11_update_clocks()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/
A Dclk_mgr.c302 void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base) in dc_destroy_clk_mgr() argument
304 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); in dc_destroy_clk_mgr()
307 switch (clk_mgr_base->ctx->asic_id.chip_family) { in dc_destroy_clk_mgr()
309 if (ASICREV_IS_SIENNA_CICHLID_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
312 if (ASICREV_IS_DIMGREY_CAVEFISH_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
315 if (ASICREV_IS_BEIGE_GOBY_P(clk_mgr_base->ctx->asic_id.hw_internal_rev)) { in dc_destroy_clk_mgr()
321 if (ASICREV_IS_VANGOGH(clk_mgr_base->ctx->asic_id.hw_internal_rev)) in dc_destroy_clk_mgr()

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