Home
last modified time | relevance | path

Searched refs:clk_pre (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/msm/dsi/phy/
A Ddsi_phy.c123 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc()
126 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc()
136 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc()
237 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc_v2()
240 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc_v2()
250 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v2()
345 timing->shared_timings.clk_pre = temp >> 1; in msm_dsi_dphy_timing_calc_v3()
348 timing->shared_timings.clk_pre = in msm_dsi_dphy_timing_calc_v3()
358 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v3()
458 timing->shared_timings.clk_pre, timing->shared_timings.clk_post, in msm_dsi_dphy_timing_calc_v4()
[all …]
A Ddsi_phy_7nm.c957 timing->shared_timings.clk_pre); in dsi_7nm_phy_enable()
979 timing->shared_timings.clk_pre); in dsi_7nm_phy_enable()
/linux/drivers/phy/
A Dphy-core-mipi-dphy.c39 cfg->clk_pre = 8000; in phy_mipi_dphy_get_default_config()
100 if (cfg->clk_pre < 8000) in phy_mipi_dphy_config_validate()
/linux/include/linux/phy/
A Dphy-mipi-dphy.h47 unsigned int clk_pre; member
/linux/drivers/phy/rockchip/
A Dphy-rockchip-inno-dsidphy.c313 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; in inno_dsidphy_mipi_mode_enable() local
367 clk_pre = DIV_ROUND_UP(cfg->clk_pre, t_txbyteclkhs); in inno_dsidphy_mipi_mode_enable()
428 T_CLK_PRE_CNT(clk_pre)); in inno_dsidphy_mipi_mode_enable()
/linux/drivers/gpu/drm/msm/dsi/
A Ddsi.h159 u32 clk_pre; member
A Ddsi_host.c861 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); in dsi_ctrl_config()
/linux/drivers/phy/amlogic/
A Dphy-meson-axg-mipi-dphy.c253 DIV_ROUND_UP(priv->config.clk_pre, temp)); in phy_meson_axg_mipi_dphy_power_on()
/linux/drivers/gpu/drm/bridge/
A Dnwl-dsi.c235 cycles = ui2bc(dsi, cfg->clk_pre); in nwl_dsi_config_host()
240 cycles += ui2bc(dsi, cfg->clk_pre); in nwl_dsi_config_host()

Completed in 22 milliseconds