Searched refs:clk_readl (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/clk/ti/
A D	dpll3xxx.c	54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken() 308 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_ssc_program() 364 v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg); in omap3_noncore_dpll_ssc_program() 399 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program() 406 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap3_noncore_dpll_program() 456 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_program() 741 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_autoidle_read() 775 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_allow_idle() 800 v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg); in omap3_dpll_deny_idle() 884 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_core_dpll_save_context() [all …]
A D	clkt_dflt.c	68 if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) in _wait_idlest_generic() 103 if (!(ti_clk_ll_ops->clk_readl(&companion_reg) & in _omap2_module_wait_ready() 228 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_enable() 234 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable() 258 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_disable() 284 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_is_enabled()
A D	apll.c	58 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable() 63 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_enable() 71 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable() 102 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_disable() 116 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_is_enabled() 247 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_is_enabled() 273 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_enable() 279 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in omap2_apll_enable() 303 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_disable() 321 v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg); in omap2_apll_set_autoidle()
A D	dpll44xx.c	49 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_allow_gatectrl() 67 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_deny_gatectrl() 129 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap4_dpll_regm4xen_recalc()
A D	clkt_iclk.c	36 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_allow_idle() 51 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_deny_idle()
A D	clkt_dpll.c	213 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_init_dpll_parent() 249 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_get_dpll_rate() 256 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap2_get_dpll_rate()
A D	clkctrl.c	158 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_enable() 169 while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_enable() 188 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_disable() 198 while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_disable() 216 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_is_enabled() 747 val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg); in ti_clk_is_in_standby()
A D	autoidle.c	129 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _allow_autoidle() 143 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _deny_autoidle()
A D	divider.c	107 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift; in ti_clk_divider_recalc_rate() 264 val = ti_clk_ll_ops->clk_readl(&divider->reg); in ti_clk_divider_set_rate() 285 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift; in clk_divider_save_context() 302 val = ti_clk_ll_ops->clk_readl(&divider->reg); in clk_divider_restore_context()
A D	mux.c	42 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent() 84 val = ti_clk_ll_ops->clk_readl(&mux->reg); in ti_clk_mux_set_parent()
A D	clk.c	115 ops->clk_readl = clk_memmap_readl; in ti_clk_setup_ll_ops() 305 ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */ in ti_clk_latch()
A D	gate.c	82 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
/linux/arch/arm/mach-omap2/
A D	clkt2xxx_dpllcore.c	139 omap_clk_ll_ops.clk_readl(&dd->mult_div1_reg); in omap2_reprogram_dpllcore()
/linux/include/linux/clk/
A D	ti.h	253 u32 (*clk_readl)(const struct clk_omap_reg *reg); member

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Last Index update Sat Jun 03 09:59:21 CST 2023