/linux/drivers/gpu/drm/amd/display/dc/ |
A D | dm_services_types.h | 82 #define DC_DECODE_PP_CLOCK_TYPE(clk_type) \ argument 83 (clk_type) == DM_PP_CLOCK_TYPE_DISPLAY_CLK ? "Display" : \ 84 (clk_type) == DM_PP_CLOCK_TYPE_ENGINE_CLK ? "Engine" : \ 85 (clk_type) == DM_PP_CLOCK_TYPE_MEMORY_CLK ? "Memory" : \ 86 (clk_type) == DM_PP_CLOCK_TYPE_DCFCLK ? "DCF" : \ 87 (clk_type) == DM_PP_CLOCK_TYPE_DCEFCLK ? "DCEF" : \ 88 (clk_type) == DM_PP_CLOCK_TYPE_SOCCLK ? "SoC" : \ 89 (clk_type) == DM_PP_CLOCK_TYPE_PIXELCLK ? "Pixel" : \ 91 (clk_type) == DM_PP_CLOCK_TYPE_DPPCLK ? "DPP" : \ 92 (clk_type) == DM_PP_CLOCK_TYPE_FCLK ? "F" : \ [all …]
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A D | dm_services.h | 191 enum dm_pp_clock_type clk_type, 196 enum dm_pp_clock_type clk_type, 201 enum dm_pp_clock_type clk_type,
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/linux/sound/soc/intel/skylake/ |
A D | skl-ssp-clk.c | 59 switch (clk_type) { in skl_get_vbus_id() 84 if (clk_type == SKL_SCLK_FS) { in skl_fill_clk_ipc() 107 u32 vbus_id, u8 clk_type, in skl_send_clk_dma_control() argument 125 if (clk_type == SKL_SCLK_FS) { in skl_send_clk_dma_control() 132 if (clk_type == SKL_SCLK) in skl_send_clk_dma_control() 181 int vbus_id, clk_type; in skl_clk_change_status() local 184 if (clk_type < 0) in skl_clk_change_status() 185 return clk_type; in skl_clk_change_status() 219 int clk_type; in skl_clk_set_rate() local 230 if (clk_type < 0) in skl_clk_set_rate() [all …]
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
A D | yellow_carp_ppt.c | 684 switch (clk_type) { in yellow_carp_get_current_clk_freq() 718 switch (clk_type) { in yellow_carp_get_dpm_level_count() 751 switch (clk_type) { in yellow_carp_get_dpm_freq_by_index() 790 switch (clk_type) { in yellow_carp_clk_dpm_is_enabled() 825 switch (clk_type) { in yellow_carp_get_dpm_ultimate_freq() 861 switch (clk_type) { in yellow_carp_get_dpm_ultimate_freq() 883 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in yellow_carp_get_dpm_ultimate_freq() 913 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) { in yellow_carp_get_dpm_ultimate_freq() 935 switch (clk_type) { in yellow_carp_set_soft_freq_limited_range() 979 switch (clk_type) { in yellow_carp_print_clk_levels() [all …]
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A D | smu_v13_0.c | 1025 switch (clk_type) { in smu_v13_0_display_clock_voltage_request() 1497 switch (clk_type) { in smu_v13_0_get_dpm_ultimate_freq() 1525 clk_type); in smu_v13_0_get_dpm_ultimate_freq() 1562 clk_type); in smu_v13_0_set_soft_freq_limited_range() 1608 clk_type); in smu_v13_0_set_hard_freq_limited_range() 1768 clk_type); in smu_v13_0_get_dpm_freq_by_index() 1813 clk_type, in smu_v13_0_set_single_dpm_table() 1822 clk_type, in smu_v13_0_set_single_dpm_table() 1856 clk_type, in smu_v13_0_get_dpm_level_range() 1865 clk_type, in smu_v13_0_get_dpm_level_range() [all …]
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
A D | vangogh_ppt.c | 541 switch (clk_type) { in vangogh_get_dpm_clk_limited() 594 switch (clk_type) { in vangogh_print_legacy_clk_levels() 649 switch (clk_type) { in vangogh_print_legacy_clk_levels() 696 switch (clk_type) { in vangogh_print_clk_levels() 758 switch (clk_type) { in vangogh_print_clk_levels() 884 switch (clk_type) { in vangogh_clk_dpm_is_enabled() 925 switch (clk_type) { in vangogh_get_dpm_ultimate_freq() 970 switch (clk_type) { in vangogh_get_dpm_ultimate_freq() 1123 switch (clk_type) { in vangogh_set_soft_freq_limited_range() 1205 switch (clk_type) { in vangogh_force_clk_levels() [all …]
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A D | smu_v11_0.c | 1107 switch (clk_type) { in smu_v11_0_display_clock_voltage_request() 1745 switch (clk_type) { in smu_v11_0_get_dpm_ultimate_freq() 1773 clk_type); in smu_v11_0_get_dpm_ultimate_freq() 1810 clk_type); in smu_v11_0_set_soft_freq_limited_range() 1856 clk_type); in smu_v11_0_set_hard_freq_limited_range() 2013 clk_type); in smu_v11_0_get_dpm_freq_by_index() 2040 clk_type, in smu_v11_0_get_dpm_level_count() 2054 clk_type, in smu_v11_0_set_single_dpm_table() 2063 clk_type, in smu_v11_0_set_single_dpm_table() 2097 clk_type, in smu_v11_0_get_dpm_level_range() [all …]
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A D | cyan_skillfish_ppt.c | 276 enum smu_clk_type clk_type, in cyan_skillfish_get_current_clk_freq() argument 281 switch (clk_type) { in cyan_skillfish_get_current_clk_freq() 307 enum smu_clk_type clk_type, in cyan_skillfish_print_clk_levels() argument 316 switch (clk_type) { in cyan_skillfish_print_clk_levels() 343 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels() 350 ret = cyan_skillfish_get_current_clk_freq(smu, clk_type, &cur_value); in cyan_skillfish_print_clk_levels()
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A D | navi10_ppt.c | 1194 enum smu_clk_type clk_type, in navi10_get_current_clk_freq_by_table() argument 1202 clk_type); in navi10_get_current_clk_freq_by_table() 1242 clk_type); in navi10_is_support_fine_grained_dpm() 1265 enum smu_clk_type clk_type, char *buf) in navi10_print_clk_levels() argument 1284 switch (clk_type) { in navi10_print_clk_levels() 1302 if (!navi10_is_support_fine_grained_dpm(smu, clk_type)) { in navi10_print_clk_levels() 1454 enum smu_clk_type clk_type, uint32_t mask) in navi10_force_clk_levels() argument 1463 switch (clk_type) { in navi10_force_clk_levels() 1471 if (navi10_is_support_fine_grained_dpm(smu, clk_type)) { in navi10_force_clk_levels() 1591 enum smu_clk_type clk_type, in navi10_get_clock_by_type_with_latency() argument [all …]
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A D | sienna_cichlid_ppt.c | 920 clk_type); in sienna_cichlid_get_current_clk_freq_by_table() 971 clk_type); in sienna_cichlid_is_support_fine_grained_dpm() 1016 switch (clk_type) { in sienna_cichlid_print_clk_levels() 1033 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) in sienna_cichlid_print_clk_levels() 1164 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) in sienna_cichlid_print_clk_levels() 1180 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) in sienna_cichlid_force_clk_levels() 1183 switch (clk_type) { in sienna_cichlid_force_clk_levels() 1216 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK)) in sienna_cichlid_force_clk_levels() 1866 enum smu_clk_type clk_type, in sienna_cichlid_get_dpm_ultimate_freq() argument 1872 if (clk_type == SMU_GFXCLK) in sienna_cichlid_get_dpm_ultimate_freq() [all …]
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/linux/drivers/clk/imx/ |
A D | clk-scu.c | 31 u8 clk_type; member 50 u8 clk_type; member 241 msg.data.req.clk = clk->clk_type; in clk_scu_recalc_rate() 315 msg.clk = clk->clk_type; in clk_scu_set_rate() 360 msg.clk = clk->clk_type; in clk_scu_set_parent() 464 clk->clk_type = clk_type; in __imx_clk_scu() 510 if (clk->clk_type == idx) in imx_scu_of_clk_src_get() 540 clk->rsrc, clk->clk_type); in imx_clk_scu_probe() 556 clk->clk_type); in imx_clk_scu_probe() 663 .clk_type = clk_type, in imx_clk_scu_alloc_dev() [all …]
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A D | clk-scu.h | 33 int num_parents, u32 rsrc_id, u8 clk_type); 37 u32 rsrc_id, u8 clk_type); 51 u8 clk_type) in imx_clk_scu() argument 53 return imx_clk_scu_alloc_dev(name, NULL, 0, rsrc_id, clk_type); in imx_clk_scu() 57 int num_parents, u32 rsrc_id, u8 clk_type) in imx_clk_scu2() argument 59 return imx_clk_scu_alloc_dev(name, parents, num_parents, rsrc_id, clk_type); in imx_clk_scu2()
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/linux/drivers/gpu/drm/amd/pm/swsmu/smu12/ |
A D | renoir_ppt.c | 201 switch (clk_type) { in renoir_get_dpm_clk_limited() 281 switch (clk_type) { in renoir_get_dpm_ultimate_freq() 316 switch (clk_type) { in renoir_get_dpm_ultimate_freq() 344 switch (clk_type) { in renoir_get_dpm_ultimate_freq() 502 switch (clk_type) { in renoir_print_clk_levels() 578 switch (clk_type) { in renoir_print_clk_levels() 687 enum smu_clk_type clk_type; in renoir_force_dpm_limit_value() local 696 clk_type = clks[i]; in renoir_force_dpm_limit_value() 714 enum smu_clk_type clk_type; in renoir_unforce_dpm_levels() local 729 clk_type = clk_feature_map[i].clk_type; in renoir_unforce_dpm_levels() [all …]
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A D | smu_v12_0.c | 212 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, in smu_v12_0_set_soft_freq_limited_range() argument 217 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) in smu_v12_0_set_soft_freq_limited_range() 220 switch (clk_type) { in smu_v12_0_set_soft_freq_limited_range()
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/linux/drivers/gpu/drm/amd/pm/swsmu/ |
A D | amdgpu_smu.c | 127 clk_type, in smu_set_soft_freq_range() 150 clk_type, in smu_get_dpm_freq_range() 387 enum smu_clk_type clk_type; in smu_restore_dpm_user_profile() local 389 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) { in smu_restore_dpm_user_profile() 1967 enum smu_clk_type clk_type; in smu_force_ppclk_levels() local 2406 enum smu_clk_type clk_type; in smu_print_ppclk_levels() local 2715 enum smu_clk_type clk_type; in smu_get_clock_by_type_with_latency() local 2726 clk_type = SMU_GFXCLK; in smu_get_clock_by_type_with_latency() 2729 clk_type = SMU_MCLK; in smu_get_clock_by_type_with_latency() 2732 clk_type = SMU_DCEFCLK; in smu_get_clock_by_type_with_latency() [all …]
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/linux/drivers/gpu/drm/amd/pm/inc/ |
A D | smu_v13_0.h | 222 int smu_v13_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 225 int smu_v13_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 229 enum smu_clk_type clk_type, 240 enum smu_clk_type clk_type, 245 enum smu_clk_type clk_type, 249 enum smu_clk_type clk_type, 253 enum smu_clk_type clk_type,
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A D | smu_v11_0.h | 264 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type, 267 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type, 271 enum smu_clk_type clk_type, 282 enum smu_clk_type clk_type, 287 enum smu_clk_type clk_type, 291 enum smu_clk_type clk_type, 295 enum smu_clk_type clk_type,
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A D | amdgpu_smu.h | 611 int (*print_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, char *buf); 619 int (*force_clk_levels)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t mask); 642 enum smu_clk_type clk_type, 1162 …int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, u… 1168 …int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t m… 1384 int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, 1387 int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
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A D | smu_v12_0.h | 58 int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
A D | amdgpu_dm_pp_smu.c | 114 enum dm_pp_clock_type clk_type, in get_default_clock_levels() argument 123 switch (clk_type) { in get_default_clock_levels() 297 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type() argument 308 dc_to_pp_clock_type(clk_type), &pp_clks)) { in dm_pp_get_clock_levels_by_type() 310 get_default_clock_levels(clk_type, dc_clks); in dm_pp_get_clock_levels_by_type() 315 pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type); in dm_pp_get_clock_levels_by_type() 341 if (clk_type == DM_PP_CLOCK_TYPE_ENGINE_CLK) { in dm_pp_get_clock_levels_by_type() 369 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_latency() argument 380 dc_to_pp_clock_type(clk_type), in dm_pp_get_clock_levels_by_type_with_latency() 393 enum dm_pp_clock_type clk_type, in dm_pp_get_clock_levels_by_type_with_voltage() argument [all …]
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/linux/drivers/phy/ |
A D | phy-xgene.c | 705 enum clk_type_t clk_type) in xgene_phy_cfg_cmu_clk_type() argument 718 if (clk_type == CLK_EXT_DIFF) { in xgene_phy_cfg_cmu_clk_type() 728 } else if (clk_type == CLK_INT_DIFF) { in xgene_phy_cfg_cmu_clk_type() 738 } else if (clk_type == CLK_INT_SING) { in xgene_phy_cfg_cmu_clk_type() 759 enum clk_type_t clk_type) in xgene_phy_sata_cfg_cmu_core() argument 805 if (clk_type == CLK_EXT_DIFF) in xgene_phy_sata_cfg_cmu_core() 1136 enum clk_type_t clk_type) in xgene_phy_cal_rdy_chk() argument 1236 enum clk_type_t clk_type) in xgene_phy_pdwn_force_vco() argument 1253 enum clk_type_t clk_type, int ssc_enable) in xgene_phy_hw_init_sata() argument 1307 xgene_phy_pdwn_force_vco(ctx, PHY_CMU, clk_type); in xgene_phy_hw_init_sata() [all …]
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/linux/drivers/input/ |
A D | evdev.c | 49 enum input_clock_type clk_type; member 146 struct timespec64 ts = ktime_to_timespec64(ev_time[client->clk_type]); in __evdev_queue_syn_dropped() 177 enum input_clock_type clk_type; in evdev_set_clk_type() local 182 clk_type = INPUT_CLK_REAL; in evdev_set_clk_type() 185 clk_type = INPUT_CLK_MONO; in evdev_set_clk_type() 188 clk_type = INPUT_CLK_BOOT; in evdev_set_clk_type() 194 if (client->clk_type != clk_type) { in evdev_set_clk_type() 195 client->clk_type = clk_type; in evdev_set_clk_type() 256 ts = ktime_to_timespec64(ev_time[client->clk_type]); in evdev_pass_values()
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/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
A D | dce120_clk_mgr.c | 98 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK; in dce12_update_clocks() 113 clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK; in dce12_update_clocks()
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/linux/drivers/nfc/s3fwrn5/ |
A D | nci.h | 44 __u8 clk_type; member
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/linux/drivers/gpu/drm/amd/amdgpu/ |
A D | atombios_crtc.h | 41 u32 freq, u8 clk_type, u8 clk_src);
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