Home
last modified time | relevance | path

Searched refs:clock (Results 1 – 25 of 3658) sorted by relevance

12345678910>>...147

/linux/arch/arm/boot/dts/
A Domap24xx-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
23 #clock-cells = <0>;
31 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
86 clock-mult = <2>;
87 clock-div = <1>;
161 clock-div = <1>;
173 clock-div = <2>;
[all …]
A Dam43xx-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
36 clock-mult = <1>;
37 clock-div = <1>;
44 clock-mult = <1>;
45 clock-div = <1>;
53 clock-div = <1>;
61 clock-div = <1>;
69 clock-div = <1>;
77 clock-div = <1>;
[all …]
A Domap3xxx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
22 #clock-cells = <0>;
43 clock-mult = <2>;
44 clock-div = <1>;
51 clock-mult = <2>;
52 clock-div = <1>;
59 clock-mult = <2>;
60 clock-div = <1>;
68 clock-div = <1>;
[all …]
A Dam33xx-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
20 clock-mult = <1>;
21 clock-div = <1>;
28 clock-mult = <1>;
29 clock-div = <1>;
36 clock-mult = <1>;
37 clock-div = <1>;
45 clock-div = <1>;
53 clock-div = <1>;
[all …]
A Domap54xx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
23 #clock-cells = <0>;
29 #clock-cells = <0>;
35 #clock-cells = <0>;
43 #clock-cells = <0>;
49 #clock-cells = <0>;
128 clock-mult = <1>;
129 clock-div = <8>;
202 clock-div = <1>;
[all …]
A Dkeystone-clocks.dtsi14 #clock-cells = <0>;
24 #clock-cells = <0>;
27 clock-div = <1>;
28 clock-mult = <1>;
36 clock-div = <1>;
37 clock-mult = <1>;
65 clock-div = <2>;
74 clock-div = <3>;
83 clock-div = <3>;
92 clock-div = <4>;
[all …]
A Ddra7xx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
21 #clock-cells = <0>;
27 #clock-cells = <0>;
33 #clock-cells = <0>;
39 #clock-cells = <0>;
45 #clock-cells = <0>;
51 #clock-cells = <0>;
57 #clock-cells = <0>;
63 #clock-cells = <0>;
[all …]
A Domap44xx-clocks.dtsi9 #clock-cells = <0>;
15 #clock-cells = <0>;
21 #clock-cells = <0>;
29 #clock-cells = <0>;
35 #clock-cells = <0>;
41 #clock-cells = <0>;
47 #clock-cells = <0>;
55 #clock-cells = <0>;
61 #clock-cells = <0>;
162 clock-div = <8>;
[all …]
A Ddm814x-clocks.dtsi10 #clock-cells = <1>;
22 #clock-cells = <1>;
33 #clock-cells = <1>;
44 #clock-cells = <1>;
55 #clock-cells = <1>;
66 #clock-cells = <1>;
77 #clock-cells = <1>;
88 #clock-cells = <1>;
99 #clock-cells = <1>;
254 clock-mult = <1>;
[all …]
A Dste-nomadik-stn8815.dtsi213 clock-div = <8>;
301 clock-id = <0>;
307 clock-id = <1>;
313 clock-id = <2>;
319 clock-id = <3>;
325 clock-id = <4>;
331 clock-id = <5>;
337 clock-id = <6>;
343 clock-id = <7>;
349 clock-id = <8>;
[all …]
A Domap36xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
17 #clock-cells = <0>;
26 #clock-cells = <0>;
35 clock-mult = <1>;
36 clock-div = <2>;
51 clock-mult = <1>;
52 clock-div = <1>;
76 clock-div = <2>;
84 clock-div = <2>;
92 clock-div = <4>;
[all …]
A Dkeystone-k2hk-clocks.dtsi10 #clock-cells = <0>;
19 #clock-cells = <0>;
27 #clock-cells = <0>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
54 #clock-cells = <0>;
64 #clock-cells = <0>;
74 #clock-cells = <0>;
84 #clock-cells = <0>;
94 #clock-cells = <0>;
[all …]
A Ddm816x-clocks.dtsi5 #clock-cells = <1>;
21 #clock-cells = <1>;
33 #clock-cells = <1>;
44 #clock-cells = <1>;
59 #clock-cells = <0>;
65 #clock-cells = <0>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
86 #clock-cells = <0>;
94 #clock-cells = <0>;
[all …]
A Dexynos5420.dtsi177 clock: clock-controller@10010000 { label
187 clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
210 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
222 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
234 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
699 clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
867 clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
876 clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
885 clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
896 clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
[all …]
A Dexynos5410.dtsi76 clock: clock-controller@10010000 { label
132 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
144 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
156 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
344 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
351 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
358 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
365 clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
398 clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
415 clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
[all …]
A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi9 #clock-cells = <0>;
12 clock-mult = <1>;
13 clock-div = <3>;
17 #clock-cells = <0>;
20 clock-mult = <1>;
21 clock-div = <5>;
56 clock-div = <3>;
64 clock-div = <4>;
72 clock-div = <6>;
80 clock-div = <1>;
[all …]
A Dkeystone-k2l-clocks.dtsi10 #clock-cells = <0>;
19 #clock-cells = <0>;
27 #clock-cells = <0>;
36 #clock-cells = <0>;
45 #clock-cells = <0>;
55 #clock-cells = <0>;
65 #clock-cells = <0>;
75 #clock-cells = <0>;
85 #clock-cells = <0>;
95 #clock-cells = <0>;
[all …]
/linux/Documentation/devicetree/bindings/clock/
A Dsocionext,uniphier-clock.yaml4 $id: http://devicetree.org/schemas/clock/socionext,uniphier-clock.yaml#
7 title: UniPhier clock controller
15 - description: System clock
27 - description: Media I/O (MIO) clock, SD clock
53 "#clock-cells":
60 - "#clock-cells"
68 clock {
70 #clock-cells = <1>;
81 clock {
83 #clock-cells = <1>;
[all …]
A Dlpc1850-cgu.txt10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
27 - #clock-cells:
34 - clock-indices:
37 - clock-output-names:
54 7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
55 8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
70 26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
71 27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
[all …]
A Dmvebu-core-clock.txt5 specify the desired clock by having the clock ID in its "clocks" phandle cell.
9 1 = cpuclk (CPU clock)
12 4 = dramclk (DDR clock)
16 1 = cpuclk (CPU clock)
18 3 = ddrclk (DDR clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
68 - #clock-cells : from common clock binding; shall be set to 1
71 - clock-output-names : from common clock binding; allows overwrite default clock
[all …]
A Dqcom,gcc-sm8350.yaml27 - description: PLL test clock source (Optional clock)
28 - description: PCIE 0 Pipe clock source (Optional clock)
29 - description: PCIE 1 Pipe clock source (Optional clock)
30 - description: UFS card Rx symbol 0 clock source (Optional clock)
31 - description: UFS card Rx symbol 1 clock source (Optional clock)
33 - description: UFS phy Rx symbol 0 clock source (Optional clock)
37 - description: USB3 phy sec pipe clock source (Optional clock)
40 clock-names:
57 '#clock-cells':
72 - clock-names
[all …]
A Dexynos5260-clock.txt18 with following clock-output-names:
52 1) "samsung,exynos5260-clock-top"
54 3) "samsung,exynos5260-clock-egl"
55 4) "samsung,exynos5260-clock-kfc"
56 5) "samsung,exynos5260-clock-g2d"
57 6) "samsung,exynos5260-clock-mif"
58 7) "samsung,exynos5260-clock-mfc"
69 - #clock-cells: should be 1.
76 to the given clock controller.
176 #clock-cells = <1>;
[all …]
A Dexynos5433-clock.txt3 The Exynos5433 clock controller generates and supplies clock to various
30 which generates global data buses clock and global peripheral buses clock.
61 - clocks: list of the clock controller input clock identifiers,
65 - clock-names: list of the clock controller input clock names,
196 #clock-cells = <0>;
204 #clock-cells = <1>;
219 #clock-cells = <1>;
228 #clock-cells = <1>;
239 #clock-cells = <1>;
245 #clock-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/clock/ti/
A Dgate.txt5 This binding uses the common clock binding[1]. This clock is
12 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
13 [2] Documentation/devicetree/bindings/clock/gpio-gate-clock.txt
18 "ti,gate-clock" - basic gate clock
19 "ti,wait-gate-clock" - gate clock which waits until clock is active before
21 "ti,dss-gate-clock" - gate clock with DSS specific hardware handling
22 "ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
29 clock
33 - #clock-cells : from common clock binding; shall be set to 0
42 gates the clock and clearing the bit ungates the clock.
[all …]
/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
A Dclock.c130 struct mlx5_clock *clock = &mdev->clock; in mlx5_update_clock_info_page() local
375 container_of(clock, struct mlx5_core_dev, clock); in mlx5_extts_configure()
432 struct mlx5_clock *clock = &mdev->clock; in find_target_cycles() local
678 struct mlx5_clock *clock = &mdev->clock; in mlx5_get_pps_caps() local
767 struct mlx5_clock *clock = &mdev->clock; in mlx5_timecounter_init() local
820 struct mlx5_clock *clock = &mdev->clock; in mlx5_init_clock_info() local
843 struct mlx5_clock *clock = &mdev->clock; in mlx5_init_timer_clock() local
860 struct mlx5_clock *clock = &mdev->clock; in mlx5_init_pps() local
871 struct mlx5_clock *clock = &mdev->clock; in mlx5_init_clock() local
888 clock->ptp = ptp_clock_register(&clock->ptp_info, in mlx5_init_clock()
[all …]

Completed in 102 milliseconds

12345678910>>...147