Searched refs:clock_cfg (Results 1 – 11 of 11) sorted by relevance
| /linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| A D | ptp.c | 127 u64 clock_cfg; in ptp_start() local
143 clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
148 clock_cfg &= ~PTP_CLOCK_CFG_EXT_CLK_IN_MASK; in ptp_start()
149 clock_cfg |= PTP_CLOCK_CFG_EXT_CLK_EN; in ptp_start()
153 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EDGE; in ptp_start()
155 clock_cfg &= ~PTP_CLOCK_CFG_TSTMP_IN_MASK; in ptp_start()
156 clock_cfg |= PTP_CLOCK_CFG_TSTMP_EN; in ptp_start()
159 clock_cfg |= PTP_CLOCK_CFG_PTP_EN; in ptp_start()
161 writeq(clock_cfg, ptp->reg_base + PTP_CLOCK_CFG); in ptp_start()
237 u64 clock_cfg; in ptp_remove() local
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| /linux/drivers/net/ethernet/cavium/common/ |
| A D | cavium_ptp.c | 226 u64 clock_cfg; in cavium_ptp_probe() local
275 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
276 clock_cfg |= PTP_CLOCK_CFG_PTP_EN; in cavium_ptp_probe()
277 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
292 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
293 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; in cavium_ptp_probe()
294 writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_probe()
314 u64 clock_cfg; in cavium_ptp_remove() local
321 clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG); in cavium_ptp_remove()
322 clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN; in cavium_ptp_remove()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 454 struct dc_clock_config *clock_cfg) in dcn2_get_clock() argument
458 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dcn2_get_clock()
459 clock_cfg->min_clock_khz = DCN_MINIMUM_DISPCLK_Khz; in dcn2_get_clock()
460 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; in dcn2_get_clock()
461 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dispclk_khz; in dcn2_get_clock()
464 clock_cfg->max_clock_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz; in dcn2_get_clock()
465 clock_cfg->min_clock_khz = DCN_MINIMUM_DPPCLK_Khz; in dcn2_get_clock()
466 clock_cfg->current_clock_khz = clk_mgr->clks.dppclk_khz; in dcn2_get_clock()
467 clock_cfg->bw_requirequired_clock_khz = context->bw_ctx.bw.dcn.clk.bw_dppclk_khz; in dcn2_get_clock()
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| A D | dcn20_clk_mgr.h | 51 struct dc_clock_config *clock_cfg);
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| /linux/drivers/spi/ |
| A D | spi-fsi.c | 356 u64 clock_cfg = 0ULL; in fsi_spi_transfer_init() local
396 rc = fsi_spi_read_reg(ctx, SPI_FSI_CLOCK_CFG, &clock_cfg); in fsi_spi_transfer_init()
400 if ((clock_cfg & (SPI_FSI_CLOCK_CFG_MM_ENABLE | in fsi_spi_transfer_init()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | clk_mgr.h | 246 struct dc_clock_config *clock_cfg);
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer.h | 186 struct dc_clock_config *clock_cfg);
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| A D | dcn10_hw_sequencer.c | 3717 struct dc_clock_config clock_cfg = {0}; in dcn10_set_clock() local
3724 context, clock_type, &clock_cfg); in dcn10_set_clock()
3726 if (clk_khz > clock_cfg.max_clock_khz) in dcn10_set_clock()
3729 if (clk_khz < clock_cfg.min_clock_khz) in dcn10_set_clock()
3732 if (clk_khz < clock_cfg.bw_requirequired_clock_khz) in dcn10_set_clock()
3752 struct dc_clock_config *clock_cfg) in dcn10_get_clock() argument
3757 dc->clk_mgr->funcs->get_clock(dc->clk_mgr, context, clock_type, clock_cfg); in dcn10_get_clock()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | hw_sequencer.h | 193 struct dc_clock_config *clock_cfg);
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc.h | 1388 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg);
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc.c | 3499 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg) in dc_get_clock() argument
3502 dc->hwss.get_clock(dc, clock_type, clock_cfg); in dc_get_clock()
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