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Searched refs:clock_limits (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c112 .clock_limits = {
274 clock_limits[i].state = i; in dcn301_update_bw_bounding_box()
280 clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn301_update_bw_bounding_box()
281 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn301_update_bw_bounding_box()
282 …clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan… in dcn301_update_bw_bounding_box()
283 clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn301_update_bw_bounding_box()
284 clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn301_update_bw_bounding_box()
285 clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; in dcn301_update_bw_bounding_box()
286 clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in dcn301_update_bw_bounding_box()
290 dcn3_01_soc.clock_limits[i] = clock_limits[i]; in dcn301_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c167 .clock_limits = {
1605 clock_limits[i] = dcn2_1_soc.clock_limits[i]; in update_bw_bounding_box()
1621 clock_limits[k].state = k; in update_bw_bounding_box()
1627 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in update_bw_bounding_box()
1628 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in update_bw_bounding_box()
1630 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in update_bw_bounding_box()
1631 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in update_bw_bounding_box()
1632 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; in update_bw_bounding_box()
1633 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in update_bw_bounding_box()
1638 dcn2_1_soc.clock_limits[i] = clock_limits[i]; in update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c136 .clock_limits = {
1250 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; in dcn303_update_bw_bounding_box()
1324 dcn3_03_soc.clock_limits[i].state = i; in dcn303_update_bw_bounding_box()
1325 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn303_update_bw_bounding_box()
1335 dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz; in dcn303_update_bw_bounding_box()
1339 dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz; in dcn303_update_bw_bounding_box()
1344 dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz; in dcn303_update_bw_bounding_box()
1345 dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz; in dcn303_update_bw_bounding_box()
1351 if (dcn3_03_soc.clock_limits[i].dram_speed_mts > 1700) in dcn303_update_bw_bounding_box()
1355 dcn3_03_soc.clock_limits[i].dcfclk_mhz = 100; in dcn303_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c154 .clock_limits = {
1320 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; in dcn302_update_bw_bounding_box()
1324 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz; in dcn302_update_bw_bounding_box()
1326 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz; in dcn302_update_bw_bounding_box()
1396 dcn3_02_soc.clock_limits[i].state = i; in dcn302_update_bw_bounding_box()
1397 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn302_update_bw_bounding_box()
1403 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn302_update_bw_bounding_box()
1407 dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz; in dcn302_update_bw_bounding_box()
1411 dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz; in dcn302_update_bw_bounding_box()
1416 dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz; in dcn302_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c234 .clock_limits = {
345 .clock_limits = {
3516 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz) in dcn20_cap_soc_clocks()
3518 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz) in dcn20_cap_soc_clocks()
3520 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz) in dcn20_cap_soc_clocks()
3522 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts) in dcn20_cap_soc_clocks()
3524 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz) in dcn20_cap_soc_clocks()
3526 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz) in dcn20_cap_soc_clocks()
3528 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz) in dcn20_cap_soc_clocks()
3530 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz) in dcn20_cap_soc_clocks()
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/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c173 .clock_limits = {
2090 clock_limits[i].state = i; in dcn31_update_bw_bounding_box()
2093 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
2100 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz; in dcn31_update_bw_bounding_box()
2103 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn31_update_bw_bounding_box()
2105 …clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_… in dcn31_update_bw_bounding_box()
2106 clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn31_update_bw_bounding_box()
2107 clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz; in dcn31_update_bw_bounding_box()
2108 clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz; in dcn31_update_bw_bounding_box()
2109 clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz; in dcn31_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dml/
A Ddisplay_mode_vba.c261 if (soc->clock_limits[i].state == mode_lib->vba.VoltageLevel) in fetch_socbb_params()
264 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
265 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
266 mode_lib->vba.DRAMSpeed = soc->clock_limits[i].dram_speed_mts; in fetch_socbb_params()
267 mode_lib->vba.FabricClock = soc->clock_limits[i].fabricclk_mhz; in fetch_socbb_params()
279 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
281 mode_lib->vba.SOCCLKPerState[i] = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
282 mode_lib->vba.PHYCLKPerState[i] = soc->clock_limits[i].phyclk_mhz; in fetch_socbb_params()
284 mode_lib->vba.MaxDppclk[i] = soc->clock_limits[i].dppclk_mhz; in fetch_socbb_params()
285 mode_lib->vba.MaxDSCCLK[i] = soc->clock_limits[i].dscclk_mhz; in fetch_socbb_params()
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A Ddisplay_mode_structs.h73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; member
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c172 .clock_limits = {
2421 max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2425 max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; in dcn30_update_bw_bounding_box()
2427 max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; in dcn30_update_bw_bounding_box()
2499 dcn3_0_soc.clock_limits[i].state = i; in dcn30_update_bw_bounding_box()
2500 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn30_update_bw_bounding_box()
2506 dcn3_0_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz; in dcn30_update_bw_bounding_box()
2508 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz; in dcn30_update_bw_bounding_box()
2511 dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz; in dcn30_update_bw_bounding_box()
2512 dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz; in dcn30_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_socbb.h79 struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; member
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_resource.c140 .clock_limits = {
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
A Ddisplay_mode_vba_20.c1260 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
A Ddisplay_mode_vba_20v2.c1320 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states].dispclk_mhz, in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn21/
A Ddisplay_mode_vba_21.c1642 mode_lib->vba.soc.clock_limits[mode_lib->vba.soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn30/
A Ddisplay_mode_vba_30.c2056 v->soc.clock_limits[mode_lib->soc.num_states - 1].dispclk_mhz, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/
A Ddisplay_mode_vba_31.c2239 v->soc.clock_limits[v->soc.num_states - 1].dispclk_mhz,

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