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Searched refs:clr (Results 1 – 25 of 216) sorted by relevance

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/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/
A Ddr_ste.c758 spec->frag = IFC_GET_CLR(fte_match_set_lyr_2_4, mask, frag, clr); in dr_ste_copy_mask_spec()
771 sizeof(raw_ip), clr); in dr_ste_copy_mask_spec()
780 sizeof(raw_ip), clr); in dr_ste_copy_mask_spec()
847 IFC_GET_CLR(fte_match_set_misc3, mask, icmpv6_header_data, clr); in dr_ste_copy_mask_misc3()
886 bool clr) in mlx5dr_ste_copy_param() argument
900 dr_ste_copy_mask_spec(buff, &set_param->outer, clr); in mlx5dr_ste_copy_param()
913 dr_ste_copy_mask_misc(buff, &set_param->misc, clr); in mlx5dr_ste_copy_param()
926 dr_ste_copy_mask_spec(buff, &set_param->inner, clr); in mlx5dr_ste_copy_param()
939 dr_ste_copy_mask_misc2(buff, &set_param->misc2, clr); in mlx5dr_ste_copy_param()
953 dr_ste_copy_mask_misc3(buff, &set_param->misc3, clr); in mlx5dr_ste_copy_param()
[all …]
/linux/include/trace/events/
A Dthp.h49 TP_PROTO(unsigned long addr, unsigned long pte, unsigned long clr, unsigned long set),
50 TP_ARGS(addr, pte, clr, set),
54 __field(unsigned long, clr)
61 __entry->clr = clr;
66 …and pte = 0x%lx clr = 0x%lx, set = 0x%lx", __entry->addr, __entry->pte, __entry->clr, __entry->set)
/linux/arch/arm/mach-rpc/
A Dirq.c75 unsigned int irq, clr, set; in rpc_init_irq() local
86 clr = IRQ_NOREQUEST; in rpc_init_irq()
90 clr |= IRQ_NOPROBE; in rpc_init_irq()
100 irq_modify_status(irq, clr, set); in rpc_init_irq()
108 irq_modify_status(irq, clr, set); in rpc_init_irq()
116 irq_modify_status(irq, clr, set); in rpc_init_irq()
123 irq_modify_status(irq, clr, set); in rpc_init_irq()
/linux/arch/sparc/lib/
A Dffs.S14 clr %o0
21 clr %o1 /* 2 */
25 1: clr %o2
31 clr %o3
34 clr %o4
40 clr %o5
/linux/drivers/clocksource/
A Dtimer-armada-370-xp.c91 static void local_timer_ctrl_clrset(u32 clr, u32 set) in local_timer_ctrl_clrset() argument
93 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset()
176 u32 clr = 0, set = 0; in armada_370_xp_timer_starting_cpu() local
181 clr = TIMER0_25MHZ; in armada_370_xp_timer_starting_cpu()
182 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_starting_cpu()
245 u32 clr = 0, set = 0; in armada_370_xp_timer_common_init() local
264 clr = TIMER0_25MHZ; in armada_370_xp_timer_common_init()
267 atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set); in armada_370_xp_timer_common_init()
268 local_timer_ctrl_clrset(clr, set); in armada_370_xp_timer_common_init()
/linux/arch/m68k/ifpsp060/src/
A Ditest.S169 clr.l %d1
379 clr.l %d0
432 clr.l (%a0)
570 clr.l (%a0)
999 clr.l %d0
1013 # clr.l %d1
1260 clr.l %d0
1435 clr.l %d0
1961 clr.l %d0
2612 clr.l %d0
[all …]
A Dilsp.S298 clr.l %d1
313 clr.w %d5
362 clr.w %d6 # word u3 left
405 clr.l %d2
421 clr.l %d1
425 clr.w %d6
463 clr.l %d4
470 clr.w %d5
571 clr.w %d1 # clear lo([2])
606 clr.l %d0
[all …]
/linux/arch/m68k/ifpsp060/
A Dos.S94 clr.l %d1 | return success
101 clr.l %d1 | return success
127 clr.l %d1 | return success
134 clr.l %d1 | return success
151 clr.l %d0 | clear whole longword
152 clr.l %d1 | assume success
187 clr.l %d1 | assume success
223 clr.l %d1 | assume success
245 clr.l %d1 | assume success
267 clr.l %d1 | assume success
[all …]
/linux/kernel/irq/
A Ddevres.c236 unsigned int clr; member
244 irq_remove_generic_chip(this->gc, this->msk, this->clr, this->set); in devm_irq_remove_generic_chip()
264 unsigned int clr, unsigned int set) in devm_irq_setup_generic_chip() argument
273 irq_setup_generic_chip(gc, msk, flags, clr, set); in devm_irq_setup_generic_chip()
277 dr->clr = clr; in devm_irq_setup_generic_chip()
/linux/drivers/net/wireless/ath/ath9k/
A Dar9003_wow.c127 u32 set, clr; in ath9k_hw_wow_apply_pattern() local
160 clr = AR_WOW_LENGTH1_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
161 REG_RMW(ah, AR_WOW_LENGTH1, set, clr); in ath9k_hw_wow_apply_pattern()
165 clr = AR_WOW_LENGTH2_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
166 REG_RMW(ah, AR_WOW_LENGTH2, set, clr); in ath9k_hw_wow_apply_pattern()
170 clr = AR_WOW_LENGTH3_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
171 REG_RMW(ah, AR_WOW_LENGTH3, set, clr); in ath9k_hw_wow_apply_pattern()
175 clr = AR_WOW_LENGTH4_MASK(pattern_count); in ath9k_hw_wow_apply_pattern()
176 REG_RMW(ah, AR_WOW_LENGTH4, set, clr); in ath9k_hw_wow_apply_pattern()
/linux/arch/powerpc/include/asm/
A Ddcr-native.h112 unsigned clr, unsigned set) in __dcri_clrset() argument
120 val = (mfdcrx(base_data) & ~clr) | set; in __dcri_clrset()
124 val = (__mfdcr(base_data) & ~clr) | set; in __dcri_clrset()
138 #define dcri_clrset(base, reg, clr, set) __dcri_clrset(DCRN_ ## base ## _CONFIG_ADDR, \ argument
140 reg, clr, set)
A Dcode-patching.h50 static inline int modify_instruction(unsigned int *addr, unsigned int clr, in modify_instruction() argument
53 return patch_instruction(addr, ppc_inst((*addr & ~clr) | set)); in modify_instruction()
56 static inline int modify_instruction_site(s32 *site, unsigned int clr, unsigned int set) in modify_instruction_site() argument
58 return modify_instruction((unsigned int *)patch_site_addr(site), clr, set); in modify_instruction_site()
/linux/arch/m68k/math-emu/
A Dfp_util.S70 2: clr.l %d0
99 clr.l %d1 | sign defaults to zero
109 clr.l (%a0)
116 clr.l (%a0)+
117 clr.l (%a0)+
118 clr.l (%a0)
142 clr.l (%a0) | low lword = 0
/linux/drivers/gpu/drm/nouveau/dispnv50/
A Dhead.c43 union nv50_head_atom_mask clr = { in nv50_head_flush_clr() local
46 if (clr.crc) nv50_crc_atomic_clr(head); in nv50_head_flush_clr()
47 if (clr.olut) head->func->olut_clr(head); in nv50_head_flush_clr()
48 if (clr.core) head->func->core_clr(head); in nv50_head_flush_clr()
49 if (clr.curs) head->func->curs_clr(head); in nv50_head_flush_clr()
400 asyh->clr.core = true; in nv50_head_atomic_check()
408 asyh->clr.curs = true; in nv50_head_atomic_check()
416 asyh->clr.olut = true; in nv50_head_atomic_check()
419 asyh->clr.olut = armh->olut.visible; in nv50_head_atomic_check()
420 asyh->clr.core = armh->core.visible; in nv50_head_atomic_check()
[all …]
A Dwndw.c128 union nv50_wndw_atom_mask clr = { in nv50_wndw_flush_clr() local
131 if (clr.sema ) wndw->func-> sema_clr(wndw); in nv50_wndw_flush_clr()
132 if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); in nv50_wndw_flush_clr()
133 if (clr.xlut ) wndw->func-> xlut_clr(wndw); in nv50_wndw_flush_clr()
134 if (clr.csc ) wndw->func-> csc_clr(wndw); in nv50_wndw_flush_clr()
135 if (clr.image) wndw->func->image_clr(wndw); in nv50_wndw_flush_clr()
414 asyw->clr.xlut = armw->xlut.handle != 0; in nv50_wndw_atomic_check_lut()
429 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check_lut()
508 if (asyw->clr.xlut && asyw->visible) in nv50_wndw_atomic_check()
510 asyw->clr.csc = armw->csc.valid; in nv50_wndw_atomic_check()
[all …]
/linux/drivers/pinctrl/
A Dpinctrl-microchip-sgpio.c167 u32 clr, set; in sgpio_configure_bitstream() local
171 clr = SGPIO_LUTON_PORT_WIDTH; in sgpio_configure_bitstream()
176 clr = SGPIO_OCELOT_PORT_WIDTH; in sgpio_configure_bitstream()
181 clr = SGPIO_SPARX5_PORT_WIDTH; in sgpio_configure_bitstream()
188 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); in sgpio_configure_bitstream()
193 u32 clr, set; in sgpio_configure_clock() local
197 clr = SGPIO_LUTON_CLK_FREQ; in sgpio_configure_clock()
201 clr = SGPIO_OCELOT_CLK_FREQ; in sgpio_configure_clock()
205 clr = SGPIO_SPARX5_CLK_FREQ; in sgpio_configure_clock()
211 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); in sgpio_configure_clock()
[all …]
/linux/arch/powerpc/include/asm/book3s/64/
A Dradix.h148 static inline unsigned long __radix_pte_update(pte_t *ptep, unsigned long clr, in __radix_pte_update() argument
160 : "r" (ptep), "r" (cpu_to_be64(set)), "r" (cpu_to_be64(clr)) in __radix_pte_update()
168 pte_t *ptep, unsigned long clr, in radix__pte_update() argument
174 old_pte = __radix_pte_update(ptep, clr, set); in radix__pte_update()
266 pmd_t *pmdp, unsigned long clr,
/linux/drivers/gpio/
A Dgpio-mmio.c491 void __iomem *clr, in bgpio_setup_io() argument
499 if (set && clr) { in bgpio_setup_io()
501 gc->reg_clr = clr; in bgpio_setup_io()
504 } else if (set && !clr) { in bgpio_setup_io()
601 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, in bgpio_init() argument
621 ret = bgpio_setup_io(gc, dat, set, clr, flags); in bgpio_init()
730 void __iomem *clr; in bgpio_pdev_probe() local
762 clr = bgpio_map(pdev, "clr", sz); in bgpio_pdev_probe()
763 if (IS_ERR(clr)) in bgpio_pdev_probe()
764 return PTR_ERR(clr); in bgpio_pdev_probe()
[all …]
/linux/arch/mips/include/asm/octeon/
A Dcvmx-gpio-defs.h296 uint64_t clr:24; member
298 uint64_t clr:24;
305 uint64_t clr:16; member
307 uint64_t clr:16;
314 uint64_t clr:20; member
316 uint64_t clr:20;
/linux/drivers/staging/media/omap4iss/
A Diss.h191 u32 offset, u32 clr) in iss_reg_clr() argument
195 iss_reg_write(iss, res, offset, v & ~clr); in iss_reg_clr()
226 u32 offset, u32 clr, u32 set) in iss_reg_update() argument
230 iss_reg_write(iss, res, offset, (v & ~clr) | set); in iss_reg_update()
/linux/arch/mips/pic32/pic32mzda/
A Dconfig.c71 u32 clr, set; in pic32_set_sdhci_adma_fifo_threshold() local
73 clr = (0x3ff << 4) | (0x3ff << 16); in pic32_set_sdhci_adma_fifo_threshold()
75 return pic32_conf_modify_atomic(PIC32_CFGCON2, clr, set); in pic32_set_sdhci_adma_fifo_threshold()
/linux/drivers/staging/sm750fb/
A Dsm750_accel.c39 u32 reg, clr; in sm750_hw_de_init() local
46 clr = DE_STRETCH_FORMAT_PATTERN_XY | in sm750_hw_de_init()
54 (read_dpr(accel, DE_STRETCH_FORMAT) & ~clr) | reg); in sm750_hw_de_init()
63 clr = DE_CONTROL_TRANSPARENCY | DE_CONTROL_TRANSPARENCY_MATCH | in sm750_hw_de_init()
67 write_dpr(accel, DE_CONTROL, read_dpr(accel, DE_CONTROL) & ~clr); in sm750_hw_de_init()
/linux/arch/sparc/include/asm/
A Dttable.h18 clr %o0; clr %o1; clr %o2; clr %o3; \
19 clr %o4; clr %o5; clr %o6; clr %o7; \
20 clr %l0; clr %l1; clr %l2; clr %l3; \
21 clr %l4; clr %l5; clr %l6; clr %l7; \
/linux/drivers/irqchip/
A Dirq-orion.c55 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in orion_irq_init() local
71 handle_level_irq, clr, 0, in orion_irq_init()
141 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; in orion_bridge_irq_init() local
158 handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE); in orion_bridge_irq_init()
/linux/arch/mips/kernel/
A Dhead.S35 .macro setup_c0_status set clr
38 or t0, ST0_KERNEL_CUMASK|\set|0x1f|\clr
39 xor t0, 0x1f|\clr

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