/linux/drivers/gpu/drm/amd/display/dc/dce120/ |
A D | dce120_hw_sequencer.c | 78 #define CNTL_ID(controller_id)\ 79 controller_id 83 static void dce120_init_pte(struct dc_context *ctx, uint8_t controller_id) 152 uint8_t controller_id, in dce120_enable_display_power_gating() argument 172 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { in dce120_enable_display_power_gating() 175 dcb, controller_id + 1, cntl); in dce120_enable_display_power_gating() 181 HW_REG_CRTC(mmCRTC0_CRTC_MASTER_UPDATE_MODE, controller_id), in dce120_enable_display_power_gating() 186 dce120_init_pte(ctx, controller_id); in dce120_enable_display_power_gating()
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/linux/drivers/gpu/drm/amd/display/dc/bios/ |
A D | command_table.h | 76 enum controller_id controller_id, 80 enum controller_id controller_id, 90 enum controller_id crtc_id,
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A D | command_table2.h | 76 enum controller_id controller_id, 80 enum controller_id controller_id, 90 enum controller_id crtc_id,
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A D | command_table2.c | 453 uint8_t controller_id; in set_pixel_clock_v7() local 460 controller_id, &controller_id)) { in set_pixel_clock_v7() 480 clk.crtc_id = controller_id; in set_pixel_clock_v7() 500 bp_params->target_pixel_clock_100hz, (int)controller_id, in set_pixel_clock_v7() 583 bp_params->controller_id, &atom_controller_id)) in set_crtc_using_dtd_timing_v3() 675 enum controller_id controller_id, 694 enum controller_id controller_id, in enable_crtc_v1() argument 771 enum controller_id crtc_id, 776 enum controller_id crtc_id, 818 enum controller_id crtc_id, in enable_disp_power_gating_v2_1() [all …]
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A D | command_table.c | 1051 uint8_t controller_id; in set_pixel_clock_v5() local 1058 bp_params->controller_id, &controller_id)) { in set_pixel_clock_v5() 1121 uint8_t controller_id; in set_pixel_clock_v6() local 1128 bp_params->controller_id, &controller_id)) { in set_pixel_clock_v6() 1213 uint8_t controller_id; in set_pixel_clock_v7() local 1986 enum controller_id controller_id, 2005 enum controller_id controller_id, in enable_crtc_v1() argument 2038 enum controller_id controller_id, 2055 enum controller_id controller_id, in enable_crtc_mem_req_v1() argument 2318 enum controller_id crtc_id, [all …]
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A D | command_table_helper2.h | 41 enum controller_id id,
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A D | command_table_helper.h | 41 enum controller_id id,
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A D | command_table_helper_struct.h | 35 bool (*controller_id_to_atom)(enum controller_id id, uint8_t *atom_id);
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A D | command_table_helper2.c | 92 enum controller_id id, in dal_cmd_table_helper_controller_id_to_atom2()
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/linux/drivers/gpu/drm/amd/display/dc/dce/ |
A D | dce_abm.c | 58 static bool dce_abm_set_pipe(struct abm *abm, uint32_t controller_id, uint32_t panel_inst) in dce_abm_set_pipe() argument 75 MASTER_COMM_CMD_REG_BYTE1, controller_id); in dce_abm_set_pipe() 90 uint32_t controller_id, in dmcu_set_backlight_level() argument 103 dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id); in dmcu_set_backlight_level() 113 if (controller_id == 0) in dmcu_set_backlight_level() 234 unsigned int controller_id, in dce_abm_set_backlight_level_pwm() argument 245 controller_id, in dce_abm_set_backlight_level_pwm()
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A D | dce_clock_source.c | 858 bp_pc_params.controller_id = pix_clk_params->controller_id; in dce110_program_pix_clk() 923 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dce112_program_pix_clk() 946 bp_pc_params.controller_id = pix_clk_params->controller_id; in dce112_program_pix_clk() 986 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; in dce110_clock_source_power_down() 1090 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dcn20_program_pix_clk() 1136 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; in dcn3_program_pix_clk()
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/linux/drivers/gpu/drm/amd/display/include/ |
A D | bios_parser_types.h | 137 enum controller_id controller_id; member 172 enum controller_id controller_id; member 220 enum controller_id controller_id; /* (Which CRTC uses this PLL) */ member
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A D | grph_object_id.h | 74 enum controller_id { enum 256 static inline enum controller_id dal_graphics_object_id_get_controller_id( in dal_graphics_object_id_get_controller_id() 260 return (enum controller_id) id.id; in dal_graphics_object_id_get_controller_id()
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/linux/drivers/gpu/drm/amd/display/dc/dce100/ |
A D | dce100_hw_sequencer.c | 74 uint8_t controller_id, in dce100_enable_display_power_gating() argument 89 if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){ in dce100_enable_display_power_gating() 92 dcb, controller_id + 1, cntl); in dce100_enable_display_power_gating() 98 HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id), in dce100_enable_display_power_gating()
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A D | dce100_hw_sequencer.h | 45 bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
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/linux/drivers/gpu/drm/amd/display/dc/dce112/ |
A D | dce112_hw_sequencer.c | 115 uint8_t controller_id, in dce112_enable_display_power_gating() argument 133 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){ in dce112_enable_display_power_gating() 136 dcb, controller_id + 1, cntl); in dce112_enable_display_power_gating() 142 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), in dce112_enable_display_power_gating()
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
A D | abm.h | 40 bool (*set_pipe)(struct abm *abm, unsigned int controller_id, unsigned int panel_inst); 48 unsigned int controller_id,
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/linux/drivers/gpu/drm/amd/display/dc/ |
A D | dc_bios_types.h | 102 enum controller_id id, 125 enum controller_id controller_id,
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/linux/drivers/scsi/aic94xx/ |
A D | aic94xx_sds.h | 66 struct controller_id { struct 85 struct controller_id contrl_id; /*PCI id to identify the controller */ argument
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/linux/drivers/gpu/drm/amd/display/dc/inc/ |
A D | clock_source.h | 92 enum controller_id controller_id; member
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/linux/drivers/gpu/drm/amd/display/dc/dce110/ |
A D | dce110_timing_generator.h | 101 enum controller_id controller_id; member
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A D | dce110_timing_generator.c | 146 result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, true); in dce110_timing_generator_enable_crtc() 238 result = tg->bp->funcs->enable_crtc(tg->bp, tg110->controller_id, false); in dce110_timing_generator_disable_crtc() 307 bp_params.controller_id = tg110->controller_id; in dce110_timing_generator_program_timing_generator() 1805 switch (tg110->controller_id) { in dce110_timing_generator_disable_vga() 2250 tg110->controller_id = CONTROLLER_ID_D0 + instance; in dce110_timing_generator_construct()
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/linux/drivers/gpu/drm/amd/display/dc/core/ |
A D | dc_surface.c | 98 uint32_t controller_id) in enable_surface_flip_reporting() argument 100 plane_state->irq_source = controller_id + DC_IRQ_SOURCE_PFLIP1 - 1; in enable_surface_flip_reporting()
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/linux/drivers/gpu/drm/amd/include/ |
A D | dm_pp_interface.h | 51 uint32_t controller_id; member
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/linux/drivers/pci/controller/dwc/ |
A D | pci-imx6.c | 74 u32 controller_id; member 411 return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; in imx6_pcie_grp_offset() 601 imx6_pcie->controller_id == 1) { in imx6_pcie_configure_type() 1077 imx6_pcie->controller_id = 1; in imx6_pcie_probe()
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