Home
last modified time | relevance | path

Searched refs:core_pll (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/video/fbdev/kyro/
A DSTG4000InitDevice.c244 u16 core_pll = 0, sub; in SetCoreClockPLL() local
284 core_pll |= ((P) | ((F - 2) << 2) | ((R - 2) << 11)); in SetCoreClockPLL()
289 tmp = ((CORE_PLL_MODE_REG_0_7 << 8) | (core_pll & 0x00FF)); in SetCoreClockPLL()
302 ((CORE_PLL_MODE_REG_8_15 << 8) | ((core_pll & 0xFF00) >> 8)); in SetCoreClockPLL()
/linux/drivers/clk/mvebu/
A Ddove-divider.c215 static const char *core_pll[] = { variable
229 clk = clk_register_fixed_rate(dev, core_pll[0], NULL, 0, 2000000000UL); in dove_divider_init()
235 core_pll, in dove_divider_init()
236 ARRAY_SIZE(core_pll), base); in dove_divider_init()

Completed in 5 milliseconds