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Searched refs:cpu_reg (Results 1 – 8 of 8) sorted by relevance

/linux/arch/arm64/kvm/hyp/nvhe/
A Dhyp-main.c28 cpu_reg(host_ctxt, 1) = __kvm_vcpu_run(kern_hyp_va(vcpu)); in handle___kvm_vcpu_run()
68 __kvm_timer_set_cntvoff(cpu_reg(host_ctxt, 1)); in handle___kvm_timer_set_cntvoff()
82 cpu_reg(host_ctxt, 1) = __vgic_v3_get_gic_config(); in handle___vgic_v3_get_gic_config()
87 cpu_reg(host_ctxt, 1) = __vgic_v3_read_vmcr(); in handle___vgic_v3_read_vmcr()
92 __vgic_v3_write_vmcr(cpu_reg(host_ctxt, 1)); in handle___vgic_v3_write_vmcr()
102 cpu_reg(host_ctxt, 1) = __kvm_get_mdcr_el2(); in handle___kvm_get_mdcr_el2()
140 cpu_reg(host_ctxt, 1) = pkvm_cpu_set_vector(slot); in handle___pkvm_cpu_set_vector()
147 cpu_reg(host_ctxt, 1) = __pkvm_host_share_hyp(pfn); in handle___pkvm_host_share_hyp()
161 cpu_reg(host_ctxt, 1) = __pkvm_prot_finalize(); in handle___pkvm_prot_finalize()
228 cpu_reg(host_ctxt, 0) = SMCCC_RET_SUCCESS; in handle_host_hcall()
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A Dpsci-relay.c74 return psci_call(cpu_reg(host_ctxt, 0), cpu_reg(host_ctxt, 1), in psci_forward()
75 cpu_reg(host_ctxt, 2), cpu_reg(host_ctxt, 3)); in psci_forward()
215 cpu_reg(host_ctxt, 0) = boot_args->r0; in kvm_host_psci_cpu_entry()
299 cpu_reg(host_ctxt, 0) = ret; in kvm_host_psci_handler()
300 cpu_reg(host_ctxt, 1) = 0; in kvm_host_psci_handler()
301 cpu_reg(host_ctxt, 2) = 0; in kvm_host_psci_handler()
302 cpu_reg(host_ctxt, 3) = 0; in kvm_host_psci_handler()
A Dsetup.c261 cpu_reg(host_ctxt, 1) = ret; in __pkvm_init_finalise()
/linux/drivers/net/ethernet/broadcom/
A Dbnx2_fw.h12 static const struct cpu_reg cpu_reg_com = {
28 static const struct cpu_reg cpu_reg_cp = {
44 static const struct cpu_reg cpu_reg_rxp = {
60 static const struct cpu_reg cpu_reg_tpat = {
76 static const struct cpu_reg cpu_reg_txp = {
A Dbnx2.c3833 load_cpu_fw(struct bnx2 *bp, const struct cpu_reg *cpu_reg, in load_cpu_fw() argument
3843 val |= cpu_reg->mode_value_halt; in load_cpu_fw()
3844 bnx2_reg_wr_ind(bp, cpu_reg->mode, val); in load_cpu_fw()
3845 bnx2_reg_wr_ind(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
3853 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3867 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3881 offset = cpu_reg->spad_base + (addr - cpu_reg->mips_view_base); in load_cpu_fw()
3890 bnx2_reg_wr_ind(bp, cpu_reg->inst, 0); in load_cpu_fw()
3893 bnx2_reg_wr_ind(bp, cpu_reg->pc, val); in load_cpu_fw()
3897 val &= ~cpu_reg->mode_value_halt; in load_cpu_fw()
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A Dbnx2.h7016 struct cpu_reg { struct
/linux/arch/arm64/kvm/hyp/include/nvhe/
A Dtrap_handler.h14 #define cpu_reg(ctxt, r) (ctxt)->regs.regs[r] macro
16 type name = (type)cpu_reg(ctxt, (reg))
/linux/Documentation/devicetree/bindings/cpufreq/
A Dnvidia,tegra20-cpufreq.txt30 cpu_reg: regulator0 {
53 cpu-supply = <&cpu_reg>;

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