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Searched refs:crtc_state (Results 1 – 25 of 254) sorted by relevance

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/linux/drivers/gpu/drm/i915/display/
A Dintel_color.c1339 crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); in i9xx_color_check()
1393 crtc_state->cgm_mode = chv_cgm_mode(crtc_state); in chv_color_check()
1399 crtc_state->preload_luts = chv_can_preload_luts(crtc_state); in chv_color_check()
1447 crtc_state->gamma_mode = ilk_gamma_mode(crtc_state); in ilk_color_check()
1449 crtc_state->csc_mode = ilk_csc_mode(crtc_state); in ilk_color_check()
1514 crtc_state->gamma_mode = ivb_gamma_mode(crtc_state); in ivb_color_check()
1516 crtc_state->csc_mode = ivb_csc_mode(crtc_state); in ivb_color_check()
1560 crtc_state->hw.ctm || crtc_state->limited_color_range; in glk_color_check()
1562 crtc_state->gamma_mode = glk_gamma_mode(crtc_state); in glk_color_check()
1617 crtc_state->gamma_mode = icl_gamma_mode(crtc_state); in icl_color_check()
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A Dintel_vrr.c80 return crtc_state->vrr.vmin + 1 - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmin_vblank_start()
85 return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); in intel_vrr_vmax_vblank_start()
125 crtc_state->vrr.vmin = vmin - 1; in intel_vrr_compute_config()
126 crtc_state->vrr.vmax = vmax; in intel_vrr_compute_config()
127 crtc_state->vrr.enable = true; in intel_vrr_compute_config()
129 crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; in intel_vrr_compute_config()
136 crtc_state->vrr.guardband = in intel_vrr_compute_config()
163 if (!crtc_state->vrr.enable) in intel_vrr_enable()
189 if (!crtc_state->vrr.enable) in intel_vrr_send_push()
218 if (!crtc_state->vrr.enable) in intel_vrr_get_config()
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A Dintel_dpll.c1115 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in ilk_crtc_compute_clock()
1122 ilk_compute_dpll(crtc_state, &crtc_state->dpll, in ilk_crtc_compute_clock()
1180 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in chv_crtc_compute_clock()
1201 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in vlv_crtc_compute_clock()
1245 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in g4x_crtc_compute_clock()
1252 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in g4x_crtc_compute_clock()
1282 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, in pnv_crtc_compute_clock()
1289 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in pnv_crtc_compute_clock()
1326 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, in i9xx_crtc_compute_clock()
1365 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, in i8xx_crtc_compute_clock()
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A Dintel_atomic.c239 crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_duplicate_state()
240 if (!crtc_state) in intel_crtc_duplicate_state()
248 if (crtc_state->hw.ctm) in intel_crtc_duplicate_state()
250 if (crtc_state->hw.gamma_lut) in intel_crtc_duplicate_state()
260 crtc_state->inherited = false; in intel_crtc_duplicate_state()
262 crtc_state->fb_bits = 0; in intel_crtc_duplicate_state()
264 crtc_state->dsb = NULL; in intel_crtc_duplicate_state()
266 return &crtc_state->uapi; in intel_crtc_duplicate_state()
310 kfree(crtc_state); in intel_crtc_destroy_state()
408 &crtc_state->scaler_state; in intel_atomic_setup_scalers()
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A Dintel_ddi.c567 crtc_state)); in intel_ddi_enable_transcoder_func()
2938 crtc_state); in trans_port_sync_stop_link_train()
3085 crtc_state, in intel_enable_ddi()
3192 int required_lanes = crtc_state ? crtc_state->lane_count : 1; in intel_ddi_update_prepare()
3198 if (crtc_state && crtc_state->hw.active) in intel_ddi_update_prepare()
3645 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in intel_ddi_get_clock()
3714 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll, in icl_ddi_tc_get_clock()
3755 if (crtc_state && intel_crtc_has_dp_encoder(crtc_state)) in intel_ddi_sync_state()
3891 crtc_state)) in intel_ddi_port_sync_transcoders()
3909 crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name); in intel_ddi_compute_config_late()
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A Dintel_ddi_buf_trans.c1220 if (crtc_state->port_clock > 540000) { in icl_get_combo_buf_trans_edp()
1249 if (crtc_state->port_clock > 270000) { in icl_get_mg_buf_trans_dp()
1274 if (crtc_state->port_clock > 270000) in ehl_get_combo_buf_trans_edp()
1301 if (crtc_state->port_clock > 270000) in jsl_get_combo_buf_trans_edp()
1384 if (crtc_state->port_clock > 270000) in dg1_get_combo_buf_trans_dp()
1400 if (crtc_state->port_clock > 540000) in dg1_get_combo_buf_trans_edp()
1431 if (crtc_state->port_clock > 270000) in rkl_get_combo_buf_trans_dp()
1477 if (crtc_state->port_clock > 270000) in adls_get_combo_buf_trans_dp()
1491 if (crtc_state->port_clock > 540000) in adls_get_combo_buf_trans_edp()
1519 if (crtc_state->port_clock > 270000) in adlp_get_combo_buf_trans_dp()
[all …]
A Dintel_vdsc.c585 if (crtc_state->bigjoiner) in intel_dsc_pps_configure()
609 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
616 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
633 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
640 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
658 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
1135 if (crtc_state->bigjoiner && !crtc_state->dsc.compression_enable) { in intel_uncompressed_joiner_enable()
1170 if (crtc_state->bigjoiner) { in intel_dsc_enable()
1200 crtc_state->bigjoiner = true; in intel_uncompressed_joiner_get_config()
1204 crtc_state->bigjoiner = true; in intel_uncompressed_joiner_get_config()
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A Dintel_panel.c207 &crtc_state->hw.adjusted_mode; in pch_panel_fitting()
218 width = crtc_state->pipe_src_w; in pch_panel_fitting()
219 height = crtc_state->pipe_src_h; in pch_panel_fitting()
228 * crtc_state->pipe_src_h; in pch_panel_fitting()
268 drm_rect_init(&crtc_state->pch_pfit.dst, in pch_panel_fitting()
270 crtc_state->pch_pfit.enabled = true; in pch_panel_fitting()
335 &crtc_state->hw.adjusted_mode; in i965_scale_aspect()
337 crtc_state->pipe_src_h; in i965_scale_aspect()
358 crtc_state->pipe_src_h; in i9xx_scale_aspect()
371 crtc_state->pipe_src_h); in i9xx_scale_aspect()
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A Dintel_dp_link_training.c370 if (intel_dp_is_uhbr(crtc_state)) in intel_dp_get_lane_adjust_train()
412 if (intel_dp_is_uhbr(crtc_state)) { in intel_dp_get_adjust_train()
417 crtc_state->lane_count, in intel_dp_get_adjust_train()
425 crtc_state->lane_count, in intel_dp_get_adjust_train()
460 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
539 crtc_state->lane_count, in intel_dp_set_signal_levels()
547 crtc_state->lane_count, in intel_dp_set_signal_levels()
854 if (intel_dp_is_uhbr(crtc_state)) in intel_dp_training_pattern()
969 crtc_state->lane_count)) { in intel_dp_link_training_channel_equalization()
1059 crtc_state->port_clock, crtc_state->lane_count); in intel_dp_link_train_phy()
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A Dintel_ddi.h24 const struct intel_crtc_state *crtc_state);
26 const struct intel_crtc_state *crtc_state);
32 const struct intel_crtc_state *crtc_state);
34 struct intel_crtc_state *crtc_state,
37 const struct intel_crtc_state *crtc_state);
41 struct intel_crtc_state *crtc_state);
44 const struct intel_crtc_state *crtc_state);
50 const struct intel_crtc_state *crtc_state);
53 const struct intel_crtc_state *crtc_state);
61 struct intel_crtc_state *crtc_state);
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A Dintel_display.c3302 memset(&crtc_state->hw, 0, sizeof(crtc_state->hw)); in intel_crtc_disable_noatomic()
3386 I915_STATE_WARN(crtc_state && crtc_state->hw.active, in intel_connector_verify_state()
6343 crtc_state->linetime = skl_linetime_wm(crtc_state); in hsw_compute_linetime_wm()
6949 crtc_state->hw.enable = crtc_state->uapi.enable; in intel_crtc_copy_uapi_to_hw_state()
6950 crtc_state->hw.active = crtc_state->uapi.active; in intel_crtc_copy_uapi_to_hw_state()
6951 crtc_state->hw.mode = crtc_state->uapi.mode; in intel_crtc_copy_uapi_to_hw_state()
6963 crtc_state->uapi.enable = crtc_state->hw.enable; in intel_crtc_copy_hw_to_uapi_state()
6964 crtc_state->uapi.active = crtc_state->hw.active; in intel_crtc_copy_hw_to_uapi_state()
7012 crtc_state->nv12_planes = crtc_state->c8_planes = crtc_state->update_planes = 0; in copy_bigjoiner_crtc_state()
11532 crtc_state->hw.enable = crtc_state->hw.active; in intel_modeset_readout_hw_state()
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A Dintel_hdmi.c711 &crtc_state->hw.adjusted_mode; in intel_hdmi_compute_avi_infoframe()
715 if (!crtc_state->has_infoframe) in intel_hdmi_compute_avi_infoframe()
718 crtc_state->infoframes.enable |= in intel_hdmi_compute_avi_infoframe()
769 if (!crtc_state->has_infoframe) in intel_hdmi_compute_spd_infoframe()
772 crtc_state->infoframes.enable |= in intel_hdmi_compute_spd_infoframe()
802 crtc_state->infoframes.enable |= in intel_hdmi_compute_hdmi_infoframe()
830 if (!crtc_state->has_infoframe) in intel_hdmi_compute_drm_infoframe()
836 crtc_state->infoframes.enable |= in intel_hdmi_compute_drm_infoframe()
1028 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
2016 &crtc_state->hw.adjusted_mode; in hdmi_deep_color_possible()
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A Dintel_psr.c797 req_ns = (72 / crtc_state->lane_count) * 1000 / (crtc_state->port_clock / 1000); in _compute_psr2_sdp_prior_scanline_indication()
861 if (crtc_state->crc_enabled) { in intel_psr2_config_valid()
925 if (crtc_state->vrr.enable && in intel_psr2_config_valid()
949 if (crtc_state->vrr.enable) in intel_psr_compute_config()
988 crtc_state->has_psr = true; in intel_psr_compute_config()
989 crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); in intel_psr_compute_config()
993 &crtc_state->psr_vsc); in intel_psr_compute_config()
1200 intel_write_dp_vsc_sdp(encoder, crtc_state, &crtc_state->psr_vsc); in intel_psr_enable_locked()
1774 if (!crtc_state->has_psr) in _intel_psr_post_plane_update()
1938 if (IS_ERR(crtc_state)) { in intel_psr_fastset_force()
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A Dskl_scaler.c98 &crtc_state->scaler_state; in skl_update_scaler()
102 &crtc_state->hw.adjusted_mode; in skl_update_scaler()
189 if (crtc_state->pch_pfit.enabled) { in skl_update_scaler_crtc()
196 return skl_update_scaler(crtc_state, !crtc_state->hw.active, in skl_update_scaler_crtc()
199 crtc_state->pipe_src_w, crtc_state->pipe_src_h, in skl_update_scaler_crtc()
201 crtc_state->pch_pfit.enabled); in skl_update_scaler_crtc()
401 &crtc_state->scaler_state; in skl_pfit_enable()
403 .x2 = crtc_state->pipe_src_w << 16, in skl_pfit_enable()
418 if (!crtc_state->pch_pfit.enabled) in skl_pfit_enable()
439 crtc_state->hw.scaling_filter); in skl_pfit_enable()
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A Dintel_dp.h50 const struct intel_crtc_state *crtc_state);
52 const struct intel_crtc_state *crtc_state,
61 bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state);
86 const struct intel_crtc_state *crtc_state,
90 const struct intel_crtc_state *crtc_state,
93 const struct intel_crtc_state *crtc_state,
96 struct intel_crtc_state *crtc_state,
109 const struct intel_crtc_state *crtc_state,
113 struct intel_crtc_state *crtc_state);
115 const struct intel_crtc_state *crtc_state);
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A Dintel_crtc.c115 struct intel_crtc_state *crtc_state; in intel_crtc_state_alloc() local
117 crtc_state = kmalloc(sizeof(*crtc_state), GFP_KERNEL); in intel_crtc_state_alloc()
119 if (crtc_state) in intel_crtc_state_alloc()
120 intel_crtc_state_reset(crtc_state, crtc); in intel_crtc_state_alloc()
122 return crtc_state; in intel_crtc_state_alloc()
128 memset(crtc_state, 0, sizeof(*crtc_state)); in intel_crtc_state_reset()
135 crtc_state->scaler_state.scaler_id = -1; in intel_crtc_state_reset()
141 struct intel_crtc_state *crtc_state; in intel_crtc_alloc() local
149 if (!crtc_state) { in intel_crtc_alloc()
154 crtc->base.state = &crtc_state->uapi; in intel_crtc_alloc()
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A Dintel_dp_mst.c59 &crtc_state->hw.adjusted_mode; in intel_dp_mst_compute_link_config()
67 crtc_state->pipe_bpp = bpp; in intel_dp_mst_compute_link_config()
75 crtc_state->pbn, in intel_dp_mst_compute_link_config()
95 &crtc_state->dp_m_n, in intel_dp_mst_compute_link_config()
97 crtc_state->dp_m_n.tu = slots; in intel_dp_mst_compute_link_config()
197 if (!crtc_state->hw.active) in intel_dp_mst_transcoder_mask()
264 if (IS_ERR(crtc_state)) { in intel_dp_mst_atomic_master_trans_check()
266 return PTR_ERR(crtc_state); in intel_dp_mst_atomic_master_trans_check()
315 if (!crtc_state || in intel_dp_mst_atomic_check()
1009 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder; in intel_dp_mst_is_master_trans()
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A Dintel_audio.c244 &crtc_state->hw.adjusted_mode; in audio_config_hdmi_pixel_clock()
276 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
279 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
536 link_clk = crtc_state->port_clock; in calc_hblank_early_prog()
537 lanes = crtc_state->lane_count; in calc_hblank_early_prog()
574 link_clk = crtc_state->port_clock; in calc_samples_room()
575 lanes = crtc_state->lane_count; in calc_samples_room()
600 if (crtc_state->dsc.compression_enable && in enable_audio_dsc_wa()
833 &crtc_state->hw.adjusted_mode; in intel_audio_codec_enable()
853 crtc_state, in intel_audio_codec_enable()
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A Dintel_dsb.c96 struct intel_dsb *dsb = crtc_state->dsb; in intel_dsb_indexed_reg_write()
97 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsb_indexed_reg_write()
173 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsb_reg_write()
178 dsb = crtc_state->dsb; in intel_dsb_reg_write()
206 struct intel_dsb *dsb = crtc_state->dsb; in intel_dsb_commit()
261 void intel_dsb_prepare(struct intel_crtc_state *crtc_state) in intel_dsb_prepare() argument
310 crtc_state->dsb = dsb; in intel_dsb_prepare()
322 void intel_dsb_cleanup(struct intel_crtc_state *crtc_state) in intel_dsb_cleanup() argument
324 if (!crtc_state->dsb) in intel_dsb_cleanup()
328 kfree(crtc_state->dsb); in intel_dsb_cleanup()
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A Dintel_cursor.c187 if (crtc_state->gamma_enable) in i845_cursor_ctl_crtc()
269 i845_cursor_ctl_crtc(crtc_state); in i845_update_cursor()
304 i845_update_cursor(plane, crtc_state, NULL); in i845_disable_cursor()
346 if (crtc_state->gamma_enable) in i9xx_cursor_ctl_crtc()
349 if (crtc_state->csc_enable) in i9xx_cursor_ctl_crtc()
505 i9xx_cursor_ctl_crtc(crtc_state); in i9xx_update_cursor()
537 skl_write_cursor_wm(plane, crtc_state); in i9xx_update_cursor()
627 struct intel_crtc_state *crtc_state = in intel_legacy_cursor_update() local
641 if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) || in intel_legacy_cursor_update()
642 crtc_state->update_pipe || crtc_state->bigjoiner) in intel_legacy_cursor_update()
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A Dintel_atomic_plane.c177 crtc_state->pixel_rate); in intel_plane_pixel_rate()
322 crtc_state->nv12_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
323 crtc_state->c8_planes &= ~BIT(plane->id); in intel_plane_set_invisible()
324 crtc_state->data_rate[plane->id] = 0; in intel_plane_set_invisible()
325 crtc_state->min_cdclk[plane->id] = 0; in intel_plane_set_invisible()
435 struct intel_crtc_state *crtc_state = in skl_next_plane_to_commit() local
492 plane->disable_plane(plane, crtc_state); in intel_disable_plane()
578 if (crtc_state->hw.enable) { in intel_atomic_plane_check_clipping()
579 clip.x2 = crtc_state->pipe_src_w; in intel_atomic_plane_check_clipping()
580 clip.y2 = crtc_state->pipe_src_h; in intel_atomic_plane_check_clipping()
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/linux/drivers/gpu/drm/gma500/
A Dgma_display.c501 kfree(gma_crtc->crtc_state); in gma_crtc_destroy()
577 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; in gma_crtc_save() local
582 if (!crtc_state) { in gma_crtc_save()
590 crtc_state->saveFP0 = REG_READ(map->fp0); in gma_crtc_save()
591 crtc_state->saveFP1 = REG_READ(map->fp1); in gma_crtc_save()
592 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save()
620 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state; in gma_crtc_restore() local
625 if (!crtc_state) { in gma_crtc_restore()
632 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE); in gma_crtc_restore()
637 REG_WRITE(map->fp0, crtc_state->saveFP0); in gma_crtc_restore()
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/linux/drivers/gpu/drm/
A Ddrm_self_refresh_helper.c78 struct drm_crtc_state *crtc_state; in drm_self_refresh_helper_entry_work() local
92 crtc_state = drm_atomic_get_crtc_state(state, crtc); in drm_self_refresh_helper_entry_work()
93 if (IS_ERR(crtc_state)) { in drm_self_refresh_helper_entry_work()
94 ret = PTR_ERR(crtc_state); in drm_self_refresh_helper_entry_work()
98 if (!crtc_state->enable) in drm_self_refresh_helper_entry_work()
110 crtc_state->active = false; in drm_self_refresh_helper_entry_work()
111 crtc_state->self_refresh_active = true; in drm_self_refresh_helper_entry_work()
190 struct drm_crtc_state *crtc_state; in drm_self_refresh_helper_alter_state() local
195 if (crtc_state->self_refresh_active) { in drm_self_refresh_helper_alter_state()
203 for_each_new_crtc_in_state(state, crtc, crtc_state, i) { in drm_self_refresh_helper_alter_state()
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/linux/drivers/gpu/drm/vkms/
A Dvkms_composer.c175 struct vkms_crtc_state *crtc_state) in compose_active_planes() argument
234 frame_start = crtc_state->frame_start; in vkms_composer_worker()
235 frame_end = crtc_state->frame_end; in vkms_composer_worker()
236 crc_pending = crtc_state->crc_pending; in vkms_composer_worker()
237 wb_pending = crtc_state->wb_pending; in vkms_composer_worker()
238 crtc_state->frame_start = 0; in vkms_composer_worker()
239 crtc_state->frame_end = 0; in vkms_composer_worker()
240 crtc_state->crc_pending = false; in vkms_composer_worker()
250 if (crtc_state->num_active_planes >= 1) { in vkms_composer_worker()
263 crtc_state); in vkms_composer_worker()
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/linux/drivers/gpu/drm/selftests/
A Dtest-drm_plane_helper.c80 const struct drm_crtc_state crtc_state = { in igt_check_plane_state() local
103 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
114 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
127 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
133 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
145 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
150 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
160 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
164 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
175 ret = drm_atomic_helper_check_plane_state(&plane_state, &crtc_state, in igt_check_plane_state()
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