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Searched refs:csr (Results 1 – 25 of 172) sorted by relevance

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/linux/arch/alpha/kernel/
A Dcore_tsunami.c181 volatile unsigned long *csr; in tsunami_pci_tbi() local
186 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
188 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
194 *csr = value; in tsunami_pci_tbi()
196 *csr; in tsunami_pci_tbi()
345 pchip->tba[2].csr = 0; in tsunami_init_one_pchip()
347 pchip->wsba[3].csr = 0; in tsunami_init_one_pchip()
350 pchip->pctl.csr |= pctl_m_mwin; in tsunami_init_one_pchip()
455 pchip->perror.csr; in tsunami_pci_clr_err_1()
456 pchip->perror.csr = 0x040; in tsunami_pci_clr_err_1()
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A Dcore_wildfire.c127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
193 temp = fast->qsd_whami.csr; in wildfire_hardware_probe()
220 temp = qsa->qsa_qbb_id.csr; in wildfire_hardware_probe()
254 temp = qsd->qsd_whami.csr; in wildfire_hardware_probe()
263 temp = qsa->qsa_qbb_pop[0].csr; in wildfire_hardware_probe()
270 temp = qsa->qsa_qbb_pop[1].csr; in wildfire_hardware_probe()
277 temp = qsa->qsa_qbb_id.csr; in wildfire_hardware_probe()
538 qsd->qsd_fault_ena.csr); in wildfire_dump_qsd_regs()
542 qsd->qsd_mem_config.csr); in wildfire_dump_qsd_regs()
544 qsd->qsd_err_sum.csr); in wildfire_dump_qsd_regs()
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A Dcore_titan.c207 volatile unsigned long *csr; in titan_pci_tbi() local
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
229 *csr = value; in titan_pci_tbi()
231 *csr; in titan_pci_tbi()
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
332 port->tba[1].csr = 0; in titan_init_one_pachip_port()
338 port->wsba[3].csr = 0; in titan_init_one_pachip_port()
341 port->pctl.csr |= pctl_m_mwin; in titan_init_one_pachip_port()
645 pctl.pctl_q_whole = port->pctl.csr; in titan_agp_configure()
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A Dsys_marvel.c174 volatile unsigned long *csr, in io7_redirect_irq() argument
179 val = *csr; in io7_redirect_irq()
183 *csr = val; in io7_redirect_irq()
185 *csr; in io7_redirect_irq()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
219 io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
230 io7->csrs->PO7_LSI_CTL[which].csr; in init_one_io7_lsi()
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A Derr_marvel.c818 err_sum |= io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
822 err_sum |= io7->ports[i].csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
843 io->io_asic_rev = io7->csrs->IO_ASIC_REV.csr; in marvel_find_io7_with_error()
844 io->io_sys_rev = io7->csrs->IO_SYS_REV.csr; in marvel_find_io7_with_error()
845 io->io7_uph = io7->csrs->IO7_UPH.csr; in marvel_find_io7_with_error()
846 io->hpi_ctl = io7->csrs->HPI_CTL.csr; in marvel_find_io7_with_error()
847 io->crd_ctl = io7->csrs->CRD_CTL.csr; in marvel_find_io7_with_error()
848 io->hei_ctl = io7->csrs->HEI_CTL.csr; in marvel_find_io7_with_error()
849 io->po7_error_sum = io7->csrs->PO7_ERROR_SUM.csr; in marvel_find_io7_with_error()
884 csrs->POx_ERR_SUM.csr; in marvel_find_io7_with_error()
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A Dcore_marvel.c61 q = ev7csr->csr; in read_ev7_csr()
73 ev7csr->csr = q; in write_ev7_csr()
184 csrs->POx_ERR_SUM.csr = -1UL; in io7_clear_errors()
185 csrs->POx_TLB_ERR.csr = -1UL; in io7_clear_errors()
187 csrs->POx_TRANS_SUM.csr = -1UL; in io7_clear_errors()
292 csrs->POx_WBASE[0].csr = in io7_init_hose()
302 csrs->POx_TBASE[1].csr = 0; in io7_init_hose()
309 csrs->POx_WBASE[2].csr = in io7_init_hose()
317 csrs->POx_WBASE[3].csr = 0; in io7_init_hose()
612 csrs->POx_SG_TBIA.csr = 0; in marvel_pci_tbi()
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/linux/arch/sparc/kernel/
A Debus.c74 u32 csr = 0; in ebus_dma_irq() local
99 u32 csr; in ebus_dma_register() local
116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
127 u32 csr; in ebus_dma_irq_enable() local
137 csr |= EBDMA_CSR_INT_EN; in ebus_dma_irq_enable()
159 u32 csr; in ebus_dma_unregister() local
179 u32 csr; in ebus_dma_request() local
208 u32 csr; in ebus_dma_prepare() local
213 csr = (EBDMA_CSR_INT_EN | in ebus_dma_prepare()
219 csr |= EBDMA_CSR_WRITE; in ebus_dma_prepare()
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/linux/drivers/usb/musb/
A Dmusb_gadget.c229 u16 fifo_count = 0, csr; in txstate() local
268 csr); in txstate()
388 csr |= MUSB_TXCSR_TXPKTRDY; in txstate()
408 u16 csr; in musb_g_tx() local
789 u16 csr; in musb_g_rx() local
915 u16 csr; in musb_gadget_enable() local
999 csr |= MUSB_TXCSR_P_ISO; in musb_gadget_enable()
1039 csr |= MUSB_RXCSR_P_ISO; in musb_gadget_enable()
1041 csr |= MUSB_RXCSR_DISNYET; in musb_gadget_enable()
1333 u16 csr; in musb_gadget_set_halt() local
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A Dmusb_gadget_ep0.c243 u16 csr; in service_zero_data_request() local
403 u16 csr; in service_zero_data_request() local
465 u16 count, csr; in ep0_rxstate() local
490 csr |= MUSB_CSR0_P_DATAEND; in ep0_rxstate()
501 musb->ackpend = csr; in ep0_rxstate()
546 csr |= MUSB_CSR0_P_DATAEND; in ep0_txstate()
556 musb->ackpend = csr; in ep0_txstate()
643 u16 csr; in musb_g_ep0_irq() local
843 handled, csr, in musb_g_ep0_irq()
997 u16 csr; in musb_g_ep0_halt() local
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A Dmusb_host.c90 u16 csr; in musb_h_tx_flush_fifo() local
124 u16 csr; in musb_h_ep0_flush_fifo() local
411 u16 csr; in musb_host_packet_rx() local
511 u16 csr; in musb_rx_reinit() local
573 u16 csr; in musb_tx_dma_set_mode_mentor() local
646 u16 csr; in musb_tx_dma_program() local
676 u16 csr; in musb_ep_program() local
715 u16 csr; in musb_ep_program() local
834 u16 csr = 0; in musb_ep_program() local
1051 u16 csr, len; in musb_h_ep0_irq() local
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A Dmusb_cppi41.c56 u16 csr; in save_rx_toggle() local
74 u16 csr; in update_rx_toggle() local
105 u16 csr; in musb_is_tx_fifo_empty() local
108 csr = musb_readw(epio, MUSB_TXCSR); in musb_is_tx_fifo_empty()
109 if (csr & MUSB_TXCSR_TXPKTRDY) in musb_is_tx_fifo_empty()
122 u16 csr; in cppi41_trans_done() local
179 csr |= MUSB_RXCSR_H_REQPKT; in cppi41_trans_done()
582 u16 csr; in cppi41_dma_channel_abort() local
593 csr &= ~MUSB_TXCSR_DMAENAB; in cppi41_dma_channel_abort()
610 csr |= MUSB_RXCSR_FLUSHFIFO; in cppi41_dma_channel_abort()
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A Dmusbhsdma.c152 u16 csr = 0; in configure_channel() local
161 csr |= MUSB_HSDMA_BURSTMODE_INCR16 in configure_channel()
178 csr); in configure_channel()
228 u16 csr; in dma_channel_abort() local
239 csr = musb_readw(mbase, offset); in dma_channel_abort()
241 musb_writew(mbase, offset, csr); in dma_channel_abort()
242 csr &= ~MUSB_TXCSR_DMAMODE; in dma_channel_abort()
243 musb_writew(mbase, offset, csr); in dma_channel_abort()
249 csr &= ~(MUSB_RXCSR_AUTOCLEAR | in dma_channel_abort()
283 u16 csr; in dma_controller_irq() local
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/linux/drivers/scsi/
A Dsun3_scsi.c196 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
203 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
243 dregs->csr |= CSR_FIFO; in sun3scsi_dma_setup()
270 dregs->csr |= CSR_FIFO; in sun3scsi_dma_setup()
348 unsigned short csr; in sun3scsi_dma_start() local
350 csr = dregs->csr; in sun3scsi_dma_start()
474 dregs->csr |= CSR_FIFO; in sun3scsi_dma_finish()
549 oldcsr = dregs->csr; in sun3_scsi_probe()
550 dregs->csr = 0; in sun3_scsi_probe()
555 dregs->csr = oldcsr; in sun3_scsi_probe()
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A Dsun3x_esp.c86 u32 csr; in sun3x_esp_dma_drain() local
89 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_drain()
90 if (!(csr & DMA_FIFO_ISDRAIN)) in sun3x_esp_dma_drain()
131 u32 csr; in sun3x_esp_send_dma_cmd() local
137 csr = dma_read32(DMA_CSR); in sun3x_esp_send_dma_cmd()
138 csr |= DMA_ENABLE; in sun3x_esp_send_dma_cmd()
140 csr |= DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
142 csr &= ~DMA_ST_WRITE; in sun3x_esp_send_dma_cmd()
143 dma_write32(csr, DMA_CSR); in sun3x_esp_send_dma_cmd()
151 u32 csr = dma_read32(DMA_CSR); in sun3x_esp_dma_error() local
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/linux/drivers/watchdog/
A Dshwdt.c85 u8 csr; in sh_wdt_start() local
97 sh_wdt_write_csr(csr); in sh_wdt_start()
110 csr |= WTCSR_TME; in sh_wdt_start()
111 csr &= ~WTCSR_RSTS; in sh_wdt_start()
112 sh_wdt_write_csr(csr); in sh_wdt_start()
116 csr &= ~RSTCSR_RSTS; in sh_wdt_start()
128 u8 csr; in sh_wdt_stop() local
135 csr &= ~WTCSR_TME; in sh_wdt_stop()
136 sh_wdt_write_csr(csr); in sh_wdt_stop()
181 u8 csr; in sh_wdt_ping() local
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/linux/drivers/usb/gadget/udc/
A Dat91_udc.c111 u32 csr; in proc_ep_show() local
132 csr, in proc_ep_show()
139 (!(csr & 0x700)) in proc_ep_show()
314 u32 csr; in read_fifo() local
341 csr |= CLR_FX; in read_fifo()
407 csr |= CLR_FX; in write_fifo()
441 csr &= ~SET_FX; in write_fifo()
739 u32 csr; in at91_ep_set_halt() local
759 csr |= CLR_FX; in at91_ep_set_halt()
1071 csr |= CLR_FX; in handle_setup()
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/linux/sound/soc/intel/atom/sst/
A Dsst_loader.c57 union config_status_reg_mrfld csr; in intel_sst_reset_dsp_mrfld() local
62 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
64 csr.full |= 0x7; in intel_sst_reset_dsp_mrfld()
68 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
70 csr.full &= ~(0x1); in intel_sst_reset_dsp_mrfld()
74 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
86 union config_status_reg_mrfld csr; in sst_start_mrfld() local
92 csr.full |= 0x7; in sst_start_mrfld()
98 csr.part.xt_snoop = 1; in sst_start_mrfld()
99 csr.full &= ~(0x5); in sst_start_mrfld()
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/linux/arch/riscv/kvm/
A Dvcpu.c57 memcpy(csr, reset_csr, sizeof(*csr)); in kvm_riscv_reset_vcpu()
476 csr->hvip &= ~mask; in kvm_riscv_vcpu_flush_interrupts()
477 csr->hvip |= val; in kvm_riscv_vcpu_flush_interrupts()
488 csr->vsie = csr_read(CSR_VSIE); in kvm_riscv_vcpu_sync_interrupts()
598 csr_write(CSR_VSIE, csr->vsie); in kvm_arch_vcpu_load()
601 csr_write(CSR_VSEPC, csr->vsepc); in kvm_arch_vcpu_load()
604 csr_write(CSR_HVIP, csr->hvip); in kvm_arch_vcpu_load()
605 csr_write(CSR_VSATP, csr->vsatp); in kvm_arch_vcpu_load()
631 csr->vsie = csr_read(CSR_VSIE); in kvm_arch_vcpu_put()
637 csr->hvip = csr_read(CSR_HVIP); in kvm_arch_vcpu_put()
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/linux/arch/sh/kernel/cpu/
A Dadc.c16 unsigned char csr; in adc_single() local
22 csr = __raw_readb(ADCSR); in adc_single()
23 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
24 __raw_writeb(csr, ADCSR); in adc_single()
27 csr = __raw_readb(ADCSR); in adc_single()
28 } while ((csr & ADCSR_ADF) == 0); in adc_single()
30 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
31 __raw_writeb(csr, ADCSR); in adc_single()
/linux/drivers/crypto/qat/qat_common/
A Dicp_qat_hal.h125 #define SET_CAP_CSR(handle, csr, val) \ argument
126 ADF_CSR_WR((handle)->hal_cap_g_ctl_csr_addr_v, csr, val)
127 #define GET_CAP_CSR(handle, csr) \ argument
128 ADF_CSR_RD((handle)->hal_cap_g_ctl_csr_addr_v, csr)
131 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & (csr))) argument
132 #define SET_AE_CSR(handle, ae, csr, val) \ argument
133 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
134 #define GET_AE_CSR(handle, ae, csr) ADF_CSR_RD(AE_CSR_ADDR(handle, ae, csr), 0) argument
A Dadf_hw_arbiter.c21 void __iomem *csr = accel_dev->transport->banks[0].csr_addr; in adf_init_arb() local
36 WRITE_CSR_ARB_SARCONFIG(csr, arb_off, arb, arb_cfg); in adf_init_arb()
42 WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, thd_2_arb_cfg[i]); in adf_init_arb()
79 void __iomem *csr; in adf_exit_arb() local
89 csr = accel_dev->transport->banks[0].csr_addr; in adf_exit_arb()
95 WRITE_CSR_ARB_SARCONFIG(csr, arb_off, i, 0); in adf_exit_arb()
99 WRITE_CSR_ARB_WT2SAM(csr, arb_off, wt_off, i, 0); in adf_exit_arb()
103 csr_ops->write_csr_ring_srv_arb_en(csr, i, 0); in adf_exit_arb()
/linux/arch/riscv/include/asm/
A Dcsr.h253 #define csr_swap(csr, val) \ argument
262 #define csr_read(csr) \ argument
265 __asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
271 #define csr_write(csr, val) \ argument
274 __asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
279 #define csr_read_set(csr, val) \ argument
288 #define csr_set(csr, val) \ argument
291 __asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
296 #define csr_read_clear(csr, val) \ argument
305 #define csr_clear(csr, val) \ argument
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/linux/drivers/pcmcia/
A Dpxa2xx_sharpsl.c58 unsigned short cpr, csr; in sharpsl_pcmcia_socket_state() local
66 csr = read_scoop_reg(scoop, SCOOP_CSR); in sharpsl_pcmcia_socket_state()
67 if (csr & 0x0004) { in sharpsl_pcmcia_socket_state()
75 csr |= SCOOP_DEV[skt->nr].keep_vs; in sharpsl_pcmcia_socket_state()
91 state->detect = (csr & 0x0004) ? 0 : 1; in sharpsl_pcmcia_socket_state()
92 state->ready = (csr & 0x0002) ? 1 : 0; in sharpsl_pcmcia_socket_state()
93 state->bvd1 = (csr & 0x0010) ? 1 : 0; in sharpsl_pcmcia_socket_state()
94 state->bvd2 = (csr & 0x0020) ? 1 : 0; in sharpsl_pcmcia_socket_state()
95 state->wrprot = (csr & 0x0008) ? 1 : 0; in sharpsl_pcmcia_socket_state()
96 state->vs_3v = (csr & 0x0040) ? 0 : 1; in sharpsl_pcmcia_socket_state()
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/linux/arch/mips/dec/
A Dkn02-irq.c30 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in unmask_kn02_irq() local
34 *csr = cached_kn02_csr; in unmask_kn02_irq()
39 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in mask_kn02_irq() local
43 *csr = cached_kn02_csr; in mask_kn02_irq()
62 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + in init_kn02_irqs() local
68 *csr = cached_kn02_csr; in init_kn02_irqs()
/linux/arch/mips/kernel/
A Dsignal.c213 unsigned int csr; in restore_msa_extcontext() local
219 err = get_user(csr, &msa->csr); in restore_msa_extcontext()
235 write_msa_csr(csr); in restore_msa_extcontext()
364 __put_user(0, csr); in protected_save_fp_context()
401 err = sig = fpcsr_pending(csr); in protected_restore_fp_context()
427 __get_user(tmp, csr); in protected_restore_fp_context()
500 unsigned int csr, enabled; in fpcsr_pending() local
502 err = __get_user(csr, fpcsr); in fpcsr_pending()
508 if (csr & enabled) { in fpcsr_pending()
509 csr &= ~enabled; in fpcsr_pending()
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