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Searched refs:csrows (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/edac/
A Dedac_mc.c129 mci->nr_csrows, mci->csrows); in edac_mc_dump_mci()
243 if (mci->csrows) { in mci_release()
245 csr = mci->csrows[row]; in mci_release()
256 kfree(mci->csrows); in mci_release()
270 mci->csrows = kcalloc(tot_csrows, sizeof(*mci->csrows), GFP_KERNEL); in edac_mc_alloc_csrows()
271 if (!mci->csrows) in edac_mc_alloc_csrows()
281 mci->csrows[row] = csr; in edac_mc_alloc_csrows()
824 struct csrow_info **csrows = mci->csrows; in edac_mc_find_csrow_by_page() local
831 struct csrow_info *csrow = csrows[i]; in edac_mc_find_csrow_by_page()
978 mci->csrows[row]->ce_count += count; in edac_inc_csrow()
[all …]
A Dpasemi_edac.c102 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
109 mci->csrows[cs]->first_page, 0, 0, in pasemi_edac_process_error_info()
132 csrow = mci->csrows[index]; in pasemi_edac_init_csrows()
A Damd76x_edac.c148 mci->csrows[row]->first_page, 0, 0, in amd76x_process_error_info()
163 mci->csrows[row]->first_page, 0, 0, in amd76x_process_error_info()
195 csrow = mci->csrows[index]; in amd76x_init_csrows()
A Dedac_mc_sysfs.c436 csrow = mci->csrows[i]; in edac_create_csrow_objects()
439 err = edac_create_csrow_object(mci, mci->csrows[i], i); in edac_create_csrow_objects()
447 if (device_is_registered(&mci->csrows[i]->dev)) in edac_create_csrow_objects()
448 device_unregister(&mci->csrows[i]->dev); in edac_create_csrow_objects()
459 if (device_is_registered(&mci->csrows[i]->dev)) in edac_delete_csrow_objects()
460 device_unregister(&mci->csrows[i]->dev); in edac_delete_csrow_objects()
673 struct csrow_info *ri = mci->csrows[row]; in mci_reset_counters_store()
803 struct csrow_info *csrow = mci->csrows[csrow_idx]; in mci_size_mb_show()
A Dcell_edac.c37 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ce()
60 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_count_ue()
130 struct csrow_info *csrow = mci->csrows[0]; in cell_edac_init_csrows()
A Di82975x_edac.c310 chan = (mci->csrows[row]->nr_channels == 1) ? 0 : info->eap & 1; in i82975x_process_error_info()
313 (1 << mci->csrows[row]->channels[chan]->dimm->grain)); in i82975x_process_error_info()
382 csrow = mci->csrows[index]; in i82975x_init_csrows()
407 dimm = mci->csrows[index]->channels[chan]->dimm; in i82975x_init_csrows()
A Daspeed_edac.c94 struct csrow_info *csrow = mci->csrows[0]; in count_rec()
127 struct csrow_info *csrow = mci->csrows[0]; in count_un_rec()
233 struct csrow_info *csrow = mci->csrows[0]; in init_csrows()
A Di82860_edac.c118 dimm = mci->csrows[row]->channels[0]->dimm; in i82860_process_error_info()
162 csrow = mci->csrows[index]; in i82860_init_csrows()
A Di3000_edac.c237 multi_chan = mci->csrows[0]->nr_channels - 1; in i3000_process_error_info()
392 struct csrow_info *csrow = mci->csrows[i]; in i3000_probe1()
A Di82875p_edac.c229 multi_chan = mci->csrows[0]->nr_channels - 1; in i82875p_process_error_info()
362 csrow = mci->csrows[index]; in i82875p_init_csrows()
A Dcpc925_edac.c337 csrow = mci->csrows[index]; in cpc925_init_csrows()
452 if (mci->csrows[rank]->first_page == 0) { in cpc925_mc_get_pfn()
460 pa = mci->csrows[rank]->first_page << PAGE_SHIFT; in cpc925_mc_get_pfn()
A Dfsl_ddr_edac.c321 csrow = mci->csrows[row_index]; in fsl_mc_check()
447 csrow = mci->csrows[index]; in fsl_ddr_init_csrows()
A Dr82600_edac.c231 csrow = mci->csrows[index]; in r82600_init_csrows()
A Di82443bxgx_edac.c197 csrow = mci->csrows[index]; in i82443bxgx_init_csrows()
A Dx38_edac.c373 struct csrow_info *csrow = mci->csrows[i]; in x38_probe1()
A De7xxx_edac.c379 csrow = mci->csrows[index]; in e7xxx_init_csrows()
A Ddmc520_edac.c460 csi = mci->csrows[row]; in dmc520_init_csrow()
A Dppc4xx_edac.c919 struct csrow_info *csi = mci->csrows[row]; in ppc4xx_edac_init_csrows()
A De752x_edac.c1096 csrow = mci->csrows[remap_csrow_index(mci, index)]; in e752x_init_csrows()
A Dsynopsys_edac.c780 csi = mci->csrows[row]; in init_csrows()
A Damd64_edac.c3250 dimm = mci->csrows[cs]->channels[umc]->dimm; in init_csrows_df()
3304 csrow = mci->csrows[i]; in init_csrows()
/linux/Documentation/admin-guide/
A Dras.rst329 There can be multiple csrows and multiple channels.
340 Memory controllers allow for several csrows, with 8 csrows being a
341 typical value. Yet, the actual number of csrows depends on the layout of
378 channel 1. Notice that there are two csrows possible on a physical DIMM.
379 These csrows are allocated their csrow assignment based on the slot into
381 Channel, the csrows cross both DIMMs.
1008 The minimum known unity is DIMMs. There are no information about csrows.
1009 As EDAC API maps the minimum unity is csrows, the driver sequentially
1010 maps channel/DIMM into different csrows.
1129 What happens here is that errors on different csrows, but at the same
/linux/include/linux/
A Dedac.h532 struct csrow_info **csrows; member

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