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Searched refs:ctrl_reg (Results 1 – 25 of 74) sorted by relevance

123

/linux/drivers/rtc/
A Drtc-pm8xxx.c105 ctrl_reg &= ~regs->alarm_en; in pm8xxx_rtc_set_time()
161 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_set_time()
223 unsigned int ctrl_reg; in pm8xxx_rtc_set_alarm() local
249 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_set_alarm()
251 ctrl_reg &= ~regs->alarm_en; in pm8xxx_rtc_set_alarm()
269 unsigned int ctrl_reg; in pm8xxx_rtc_read_alarm() local
306 unsigned int ctrl_reg; in pm8xxx_rtc_alarm_irq_enable() local
316 ctrl_reg |= regs->alarm_en; in pm8xxx_rtc_alarm_irq_enable()
353 unsigned int ctrl_reg; in pm8xxx_alarm_trigger() local
367 ctrl_reg &= ~regs->alarm_en; in pm8xxx_alarm_trigger()
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/linux/drivers/watchdog/
A Dmachzwd.c188 unsigned int ctrl_reg = 0; in zf_timer_off() local
196 ctrl_reg = zf_get_control(); in zf_timer_off()
199 zf_set_control(ctrl_reg); in zf_timer_off()
211 unsigned int ctrl_reg = 0; in zf_timer_on() local
227 ctrl_reg = zf_get_control(); in zf_timer_on()
229 zf_set_control(ctrl_reg); in zf_timer_on()
238 unsigned int ctrl_reg = 0; in zf_ping() local
252 ctrl_reg |= RESET_WD1; in zf_ping()
253 zf_set_control(ctrl_reg); in zf_ping()
256 ctrl_reg &= ~(RESET_WD1); in zf_ping()
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/linux/drivers/clk/microchip/
A Dclk-core.c91 void __iomem *ctrl_reg; member
185 v = readl(pb->ctrl_reg); in pbclk_set_rate()
191 writel(v, pb->ctrl_reg); in pbclk_set_rate()
226 pbclk->ctrl_reg = desc->ctrl_reg + core->iobase; in pic32_periph_clk_register()
240 void __iomem *ctrl_reg; member
365 v = readl(refo->ctrl_reg); in roclk_recalc_rate()
570 refo->ctrl_reg = data->ctrl_reg + core->iobase; in pic32_refo_clk_register()
582 void __iomem *ctrl_reg; member
652 v = readl(pll->ctrl_reg); in spll_clk_recalc_rate()
702 v = readl(pll->ctrl_reg); in spll_clk_set_rate()
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A Dclk-core.h21 const u32 ctrl_reg; member
38 const u32 ctrl_reg; member
45 const u32 ctrl_reg; member
/linux/drivers/bluetooth/
A Dbluecard_cs.c79 unsigned char ctrl_reg; member
265 info->ctrl_reg |= REG_CONTROL_RTS; in bluecard_write_wakeup()
307 info->ctrl_reg &= ~0x03; in bluecard_write_wakeup()
308 info->ctrl_reg |= baud_reg; in bluecard_write_wakeup()
312 info->ctrl_reg &= ~REG_CONTROL_RTS; in bluecard_write_wakeup()
512 info->ctrl_reg &= ~REG_CONTROL_INTERRUPT; in bluecard_interrupt()
546 info->ctrl_reg |= REG_CONTROL_INTERRUPT; in bluecard_interrupt()
744 info->ctrl_reg |= REG_CONTROL_INTERRUPT; in bluecard_open()
749 info->ctrl_reg |= REG_CONTROL_RTS; in bluecard_open()
753 info->ctrl_reg |= 0x03; in bluecard_open()
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/linux/drivers/pci/hotplug/
A Dcpqphp.h108 struct ctrl_reg { /* offset */ struct
140 SLOT_RST = offsetof(struct ctrl_reg, slot_RST), argument
141 SLOT_ENABLE = offsetof(struct ctrl_reg, slot_enable),
142 MISC = offsetof(struct ctrl_reg, misc),
143 LED_CONTROL = offsetof(struct ctrl_reg, led_control),
145 INT_MASK = offsetof(struct ctrl_reg, int_mask),
146 CTRL_RESERVED0 = offsetof(struct ctrl_reg, reserved0),
147 CTRL_RESERVED1 = offsetof(struct ctrl_reg, reserved1),
157 SLOT_MASK = offsetof(struct ctrl_reg, slot_mask),
161 SLOT_SERR = offsetof(struct ctrl_reg, slot_SERR),
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A Dshpchp.h177 struct ctrl_reg { struct
195 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset), argument
196 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
197 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
198 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
200 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
202 CMD = offsetof(struct ctrl_reg, cmd),
203 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
204 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
205 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
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/linux/drivers/ntb/hw/epf/
A Dntb_hw_epf.c75 void __iomem *ctrl_reg; member
106 writel(argument, ndev->ctrl_reg + NTB_EPF_ARGUMENT); in ntb_epf_send_command()
107 writel(command, ndev->ctrl_reg + NTB_EPF_COMMAND); in ntb_epf_send_command()
112 status = readw(ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
130 writew(0, ndev->ctrl_reg + NTB_EPF_CMD_STATUS); in ntb_epf_send_command()
198 status = readw(ndev->ctrl_reg + NTB_EPF_LINK_STATUS); in ntb_epf_link_is_up()
214 offset = readl(ndev->ctrl_reg + NTB_EPF_SPAD_OFFSET); in ntb_epf_spad_read()
217 return readl(ndev->ctrl_reg + offset); in ntb_epf_spad_read()
234 writel(val, ndev->ctrl_reg + offset); in ntb_epf_spad_write()
597 if (!ndev->ctrl_reg) { in ntb_epf_init_pci()
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/linux/drivers/spi/
A Dspi-cadence.c152 u32 ctrl_reg = CDNS_SPI_CR_DEFAULT; in cdns_spi_init_hw() local
155 ctrl_reg |= CDNS_SPI_CR_PERI_SEL; in cdns_spi_init_hw()
165 cdns_spi_write(xspi, CDNS_SPI_CR, ctrl_reg); in cdns_spi_init_hw()
177 u32 ctrl_reg; in cdns_spi_chipselect() local
183 ctrl_reg |= CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
186 ctrl_reg &= ~CDNS_SPI_CR_SSCTRL; in cdns_spi_chipselect()
208 u32 ctrl_reg, new_ctrl_reg; in cdns_spi_config_clock_mode() local
211 ctrl_reg = new_ctrl_reg; in cdns_spi_config_clock_mode()
220 if (new_ctrl_reg != ctrl_reg) { in cdns_spi_config_clock_mode()
251 u32 ctrl_reg, baud_rate_val; in cdns_spi_config_clock_freq() local
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A Dspi-jcore.c44 static int jcore_spi_wait(void __iomem *ctrl_reg) in jcore_spi_wait() argument
49 if (!(readl(ctrl_reg) & JCORE_SPI_STAT_BUSY)) in jcore_spi_wait()
59 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_program() local
61 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_program()
65 writel(hw->cs_reg | hw->speed_reg, ctrl_reg); in jcore_spi_program()
102 void __iomem *ctrl_reg = hw->base + CTRL_REG; in jcore_spi_txrx() local
120 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
124 writel(xmit, ctrl_reg); in jcore_spi_txrx()
126 if (jcore_spi_wait(ctrl_reg)) in jcore_spi_txrx()
/linux/drivers/net/wireless/st/cw1200/
A Dbh.c173 u16 *ctrl_reg) in cw1200_bh_read_ctrl_reg() argument
178 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
181 ST90TDS_CONTROL_REG_ID, ctrl_reg); in cw1200_bh_read_ctrl_reg()
191 u16 ctrl_reg; in cw1200_device_wakeup() local
215 if (ctrl_reg & ST90TDS_CONT_RDY_BIT) { in cw1200_device_wakeup()
233 uint16_t *ctrl_reg, in cw1200_bh_rx_helper() argument
254 read_len, *ctrl_reg); in cw1200_bh_rx_helper()
288 *ctrl_reg = __le16_to_cpu( in cw1200_bh_rx_helper()
419 u16 ctrl_reg = 0; in cw1200_bh() local
547 if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) { in cw1200_bh()
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/linux/drivers/clk/hisilicon/
A Dclk-hix5hd2.c136 u32 ctrl_reg; member
148 void __iomem *ctrl_reg; member
174 val = readl_relaxed(clk->ctrl_reg); in clk_ether_prepare()
176 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
178 writel_relaxed(val, clk->ctrl_reg); in clk_ether_prepare()
203 val = readl_relaxed(clk->ctrl_reg); in clk_ether_unprepare()
205 writel_relaxed(val, clk->ctrl_reg); in clk_ether_unprepare()
218 val = readl_relaxed(clk->ctrl_reg); in clk_complex_enable()
221 writel_relaxed(val, clk->ctrl_reg); in clk_complex_enable()
236 val = readl_relaxed(clk->ctrl_reg); in clk_complex_disable()
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/linux/drivers/phy/marvell/
A Dphy-berlin-sata.c65 static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg, in phy_berlin_sata_reg_setbits() argument
71 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR); in phy_berlin_sata_reg_setbits()
74 regval = readl(ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
77 writel(regval, ctrl_reg + PORT_VSR_DATA); in phy_berlin_sata_reg_setbits()
84 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80); in phy_berlin_sata_power_on() local
104 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01, in phy_berlin_sata_power_on()
109 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25, in phy_berlin_sata_power_on()
113 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23, in phy_berlin_sata_power_on()
117 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02, in phy_berlin_sata_power_on()
121 regval = readl(ctrl_reg + PORT_SCR_CTL); in phy_berlin_sata_power_on()
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/linux/drivers/clocksource/
A Dtimer-cadence-ttc.c112 u32 ctrl_reg; in ttc_set_interval() local
115 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
116 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
117 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
125 ctrl_reg |= CNT_CNTRL_RESET; in ttc_set_interval()
126 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK; in ttc_set_interval()
127 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET); in ttc_set_interval()
196 u32 ctrl_reg; in ttc_shutdown() local
199 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK; in ttc_shutdown()
218 u32 ctrl_reg; in ttc_resume() local
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/linux/drivers/staging/wfx/
A Dbh.c141 int ctrl_reg, piggyback; in bh_work_rx() local
146 ctrl_reg = piggyback; in bh_work_rx()
148 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, 0); in bh_work_rx()
150 ctrl_reg = 0; in bh_work_rx()
151 if (!(ctrl_reg & CTRL_NEXT_LEN_MASK)) in bh_work_rx()
154 len = (ctrl_reg & CTRL_NEXT_LEN_MASK) * 2; in bh_work_rx()
163 ctrl_reg = atomic_xchg(&wdev->hif.ctrl_reg, piggyback); in bh_work_rx()
165 if (ctrl_reg) in bh_work_rx()
167 ctrl_reg, piggyback); in bh_work_rx()
274 prev = atomic_xchg(&wdev->hif.ctrl_reg, cur); in wfx_bh_request_rx()
/linux/drivers/misc/ibmasm/
A Dlowlevel.h53 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_enable_interrupts() local
54 writel( readl(ctrl_reg) & ~mask, ctrl_reg); in ibmasm_enable_interrupts()
59 void __iomem *ctrl_reg = base_address + INTR_CONTROL_REGISTER; in ibmasm_disable_interrupts() local
60 writel( readl(ctrl_reg) | mask, ctrl_reg); in ibmasm_disable_interrupts()
/linux/drivers/net/ethernet/intel/ixgb/
A Dixgb_hw.c49 u32 ctrl_reg; in ixgb_mac_reset() local
51 ctrl_reg = IXGB_CTRL0_RST | in ixgb_mac_reset()
64 IXGB_WRITE_REG(hw, CTRL0, ctrl_reg); in ixgb_mac_reset()
89 return ctrl_reg; in ixgb_mac_reset()
100 u32 ctrl_reg; in ixgb_adapter_stop() local
137 ctrl_reg = ixgb_mac_reset(hw); in ixgb_adapter_stop()
146 return ctrl_reg & IXGB_CTRL0_RST; in ixgb_adapter_stop()
613 u32 ctrl_reg; in ixgb_setup_fc() local
637 ctrl_reg |= (IXGB_CTRL0_CMDC); in ixgb_setup_fc()
643 ctrl_reg |= (IXGB_CTRL0_RPE); in ixgb_setup_fc()
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/linux/drivers/input/rmi4/
A Drmi_f30.c275 u8 *ctrl_reg = f30->ctrl_regs; in rmi_f30_initialize() local
300 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
303 sizeof(u8), &ctrl_reg); in rmi_f30_initialize()
307 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
310 f30->register_count, &ctrl_reg); in rmi_f30_initialize()
319 &ctrl_reg); in rmi_f30_initialize()
325 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
331 f30->gpioled_count, &ctrl_reg); in rmi_f30_initialize()
339 sizeof(u8), &ctrl_reg); in rmi_f30_initialize()
344 sizeof(u8), &ctrl_reg); in rmi_f30_initialize()
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/linux/drivers/fpga/
A Dsocfpga.c337 u32 ctrl_reg; in socfpga_fpga_cfg_mode_set() local
346 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_cfg_mode_set()
347 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CDRATIO_MASK; in socfpga_fpga_cfg_mode_set()
348 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_CFGWDTH_MASK; in socfpga_fpga_cfg_mode_set()
349 ctrl_reg |= cfgmgr_modes[mode].ctrl; in socfpga_fpga_cfg_mode_set()
352 ctrl_reg &= ~SOCFPGA_FPGMGR_CTL_NCE; in socfpga_fpga_cfg_mode_set()
353 socfpga_fpga_writel(priv, SOCFPGA_FPGMGR_CTL_OFST, ctrl_reg); in socfpga_fpga_cfg_mode_set()
361 u32 ctrl_reg, status; in socfpga_fpga_reset() local
378 ctrl_reg = socfpga_fpga_readl(priv, SOCFPGA_FPGMGR_CTL_OFST); in socfpga_fpga_reset()
379 ctrl_reg |= SOCFPGA_FPGMGR_CTL_NCFGPULL; in socfpga_fpga_reset()
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/linux/drivers/i2c/busses/
A Di2c-cadence.c206 u32 ctrl_reg; member
581 unsigned int ctrl_reg; in cdns_i2c_mrecv() local
593 ctrl_reg = cdns_i2c_readreg(CDNS_I2C_CR_OFFSET); in cdns_i2c_mrecv()
606 ctrl_reg |= CDNS_I2C_CR_HOLD; in cdns_i2c_mrecv()
676 unsigned int ctrl_reg; in cdns_i2c_msend() local
685 ctrl_reg &= ~CDNS_I2C_CR_RW; in cdns_i2c_msend()
686 ctrl_reg |= CDNS_I2C_CR_CLR_FIFO; in cdns_i2c_msend()
693 ctrl_reg |= CDNS_I2C_CR_HOLD; in cdns_i2c_msend()
1068 unsigned int ctrl_reg; in cdns_i2c_setclk() local
1076 ctrl_reg = id->ctrl_reg; in cdns_i2c_setclk()
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/linux/drivers/tty/serial/
A Dxilinx_uartps.c496 u32 ctrl_reg; in cdns_uart_clk_notifier_cb() local
526 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
528 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_clk_notifier_cb()
697 unsigned int ctrl_reg, mode_reg; in cdns_uart_set_termios() local
702 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_set_termios()
704 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_set_termios()
723 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_set_termios()
725 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_set_termios()
735 ctrl_reg = readl(port->membase + CDNS_UART_CR); in cdns_uart_set_termios()
738 writel(ctrl_reg, port->membase + CDNS_UART_CR); in cdns_uart_set_termios()
[all …]
/linux/drivers/regulator/
A Dvctrl-regulator.c326 struct regulator *ctrl_reg) in vctrl_init_vtable() argument
335 n_voltages = regulator_count_voltages(ctrl_reg); in vctrl_init_vtable()
341 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
361 ctrl_uV = regulator_list_voltage(ctrl_reg, i); in vctrl_init_vtable()
453 struct regulator *ctrl_reg; in vctrl_probe() local
469 if (IS_ERR(ctrl_reg)) in vctrl_probe()
470 return PTR_ERR(ctrl_reg); in vctrl_probe()
480 if ((regulator_get_linear_step(ctrl_reg) == 1) || in vctrl_probe()
498 ret = vctrl_init_vtable(pdev, ctrl_reg); in vctrl_probe()
503 ctrl_uV = regulator_get_voltage(ctrl_reg); in vctrl_probe()
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/linux/drivers/media/platform/davinci/
A Dvpif.h399 u32 ctrl_reg; in disable_raw_feature() local
401 ctrl_reg = VPIF_CH0_CTRL; in disable_raw_feature()
403 ctrl_reg = VPIF_CH1_CTRL; in disable_raw_feature()
406 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in disable_raw_feature()
408 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in disable_raw_feature()
413 u32 ctrl_reg; in enable_raw_feature() local
415 ctrl_reg = VPIF_CH0_CTRL; in enable_raw_feature()
417 ctrl_reg = VPIF_CH1_CTRL; in enable_raw_feature()
420 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT); in enable_raw_feature()
422 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT); in enable_raw_feature()
/linux/drivers/hwmon/
A Daspeed-pwm-tacho.c207 u32 ctrl_reg; member
218 .ctrl_reg = ASPEED_PTCR_TYPEM_CTRL,
245 u32 ctrl_reg; member
258 .ctrl_reg = ASPEED_PTCR_CTRL,
269 .ctrl_reg = ASPEED_PTCR_CTRL,
280 .ctrl_reg = ASPEED_PTCR_CTRL,
291 .ctrl_reg = ASPEED_PTCR_CTRL,
302 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
313 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
324 .ctrl_reg = ASPEED_PTCR_CTRL_EXT,
[all …]
/linux/drivers/mmc/host/
A Dmvsdio.c602 u32 ctrl_reg = 0; in mvsd_set_ios() local
624 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; in mvsd_set_ios()
625 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; in mvsd_set_ios()
628 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; in mvsd_set_ios()
629 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; in mvsd_set_ios()
632 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; in mvsd_set_ios()
647 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; in mvsd_set_ios()
650 host->ctrl = ctrl_reg; in mvsd_set_ios()
651 mvsd_write(MVSD_HOST_CTRL, ctrl_reg); in mvsd_set_ios()
653 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ? in mvsd_set_ios()
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