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Searched refs:cycles (Results 1 – 25 of 388) sorted by relevance

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/linux/arch/x86/lib/
A Ddelay.c63 static void delay_tsc(u64 cycles) in delay_tsc() argument
73 if ((now - bclock) >= cycles) in delay_tsc()
91 cycles -= (now - bclock); in delay_tsc()
105 static void delay_halt_tpause(u64 start, u64 cycles) in delay_halt_tpause() argument
107 u64 until = start + cycles; in delay_halt_tpause()
129 delay = min_t(u64, MWAITX_MAX_WAIT_CYCLES, cycles); in delay_halt_mwaitx()
151 u64 start, end, cycles = __cycles; in delay_halt() local
157 if (!cycles) in delay_halt()
163 delay_halt_fn(start, cycles); in delay_halt()
166 if (cycles <= end - start) in delay_halt()
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/linux/tools/perf/dlfilters/
A Ddlfilter-show-cycles.c19 static __u64 cycles[MAX_CPU][MAX_ENTRY]; variable
30 __u64 cycles[MAX_ENTRY]; member
77 e->cycles[pos] += cnt; in add_entry()
92 cycles[cpu][pos] += sample->cyc_cnt; in filter_event_early()
98 static void print_vals(__u64 cycles, __u64 delta) in print_vals() argument
101 printf("%10llu %10llu ", cycles, delta); in print_vals()
103 printf("%10llu %10s ", cycles, ""); in print_vals()
115 print_vals(cycles[cpu][pos], cycles[cpu][pos] - cycles_rpt[cpu][pos]); in filter_event()
116 cycles_rpt[cpu][pos] = cycles[cpu][pos]; in filter_event()
124 print_vals(e->cycles[pos], e->cycles[pos] - e->cycles_rpt[pos]); in filter_event()
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/linux/drivers/memory/
A Djz4780-nemc.c163 uint32_t smcr, val, cycles; in jz4780_nemc_configure_bank() local
212 val, cycles); in jz4780_nemc_configure_bank()
216 smcr |= cycles << NEMC_SMCR_TAS_SHIFT; in jz4780_nemc_configure_bank()
224 val, cycles); in jz4780_nemc_configure_bank()
228 smcr |= cycles << NEMC_SMCR_TAH_SHIFT; in jz4780_nemc_configure_bank()
234 if (cycles > 31) { in jz4780_nemc_configure_bank()
236 val, cycles); in jz4780_nemc_configure_bank()
246 if (cycles > 31) { in jz4780_nemc_configure_bank()
248 val, cycles); in jz4780_nemc_configure_bank()
258 if (cycles > 63) { in jz4780_nemc_configure_bank()
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/linux/drivers/gpu/drm/i915/gt/
A Dselftest_gt_pm.c42 u32 cycles[5]; in measure_clocks() local
47 cycles[i] = -ENGINE_READ_FW(engine, RING_TIMESTAMP); in measure_clocks()
53 cycles[i] += ENGINE_READ_FW(engine, RING_TIMESTAMP); in measure_clocks()
58 sort(cycles, 5, sizeof(*cycles), cmp_u32, NULL); in measure_clocks()
59 *out_cycles = (cycles[1] + 2 * cycles[2] + cycles[3]) / 4; in measure_clocks()
103 u32 cycles; in live_gt_clocks() local
111 measure_clocks(engine, &cycles, &dt); in live_gt_clocks()
113 time = intel_gt_clock_interval_to_ns(engine->gt, cycles); in live_gt_clocks()
117 engine->name, cycles, time, dt, expected, in live_gt_clocks()
127 if (9 * expected < 8 * cycles || 8 * expected > 9 * cycles) { in live_gt_clocks()
/linux/Documentation/devicetree/bindings/bus/
A Dqcom,ebi2.txt34 FIXME: the manual mentions "write precharge cycles" and "precharge cycles".
77 - qcom,xmem-recovery-cycles: recovery cycles is the time the memory continues to
82 - qcom,xmem-write-hold-cycles: write hold cycles, these are extra cycles
86 - qcom,xmem-write-delta-cycles: initial latency for write cycles inserted for
88 - qcom,xmem-read-delta-cycles: initial latency for read cycles inserted for the
90 - qcom,xmem-write-wait-cycles: number of wait cycles for every write access, 0=1
92 - qcom,xmem-read-wait-cycles: number of wait cycles for every read access, 0=1
99 - qcom,xmem-adv-to-oe-recovery-cycles: the number of cycles elapsed before an OE
102 - qcom,xmem-read-hold-cycles: the length in cycles of the first segment of a
131 qcom,xmem-recovery-cycles = <0>;
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A Dintel,ixp4xx-expansion-bus-controller.yaml62 description: Address timing, extend address phase with n cycles.
67 description: Setup chip select timing, extend setup phase with n cycles.
72 description: Strobe timing, extend strobe phase with n cycles.
77 description: Hold timing, extend hold phase with n cycles.
82 description: Recovery timing, extend recovery phase with n cycles.
87 description: The type of cycles to use on the expansion bus for this
88 chip select. 0 = Intel cycles, 1 = Motorola cycles, 2 = HPI cycles.
113 description: Enable write cycles.
/linux/tools/perf/Documentation/
A Dintel-hybrid.txt51 For example, count the 'cycles' event on core cpus.
53 perf stat -e cpu_core/cycles/
129 6,744,979 cpu_core/cycles/
130 1,965,552 cpu_atom/cycles/
132 The first 'cycles' is core event, the second 'cycles' is atom event.
143 perf stat -e cycles \-- taskset -c 16 ./triad_loop
192 cpu_core/cycles/,
193 cpu_atom/cycles/,
205 perf stat -e cpu_core/cycles/
206 perf stat -e cpu_atom/cycles/
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A Dperf-daemon.txt120 [session-cycles]
136 [603350:cycles] perf record -m 10M -e cycles --overwrite --switch-output -a
149 [603350:cycles] perf record -m 10M -e cycles --overwrite --switch-output -a
150 base: /opt/perfdata/session-cycles
151 output: /opt/perfdata/session-cycles/output
153 ack: /opt/perfdata/session-cycles/ack
173 OK cycles
179 # perf daemon signal --session cycles
180 signal 12 sent to session 'cycles [603452]'
182 # tail -2 /opt/perfdata/session-cycles/output
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A Dperf.data-directory-format.txt51 Samples for 'cycles' event do not have CPU attribute set. Skipping 'cpu' field.
55 … perf 15316 2060795.480902: 1 cycles: ffffffffa2caa548 native_write_msr+0x8 (vmlinux)
56 … perf 15316 2060795.480906: 1 cycles: ffffffffa2caa548 native_write_msr+0x8 (vmlinux)
57 … perf 15316 2060795.480908: 7 cycles: ffffffffa2caa548 native_write_msr+0x8 (vmlinux)
58 … perf 15316 2060795.480910: 119 cycles: ffffffffa2caa54a native_write_msr+0xa (vmlinux)
59 …perf 15316 2060795.480912: 2109 cycles: ffffffffa2c9b7b0 native_apic_msr_write+0x0 (vmlinux)
60 …perf 15316 2060795.480914: 37606 cycles: ffffffffa2f121fe perf_event_addr_filters_exec+0x2e …
61 …uname 15316 2060795.480924: 588287 cycles: ffffffffa303a56d page_counter_try_charge+0x6d (vml…
62 … uname 15316 2060795.481067: 2261945 cycles: ffffffffa301438f kmem_cache_free+0x4f (vmlinux)
63 …uname 15316 2060795.481643: 2172167 cycles: 7f1a48c393c0 _IO_un_link+0x0 (/lib/x86_64-linu…
/linux/Documentation/devicetree/bindings/mtd/
A Dfsmc-nand.txt15 byte 0 TCLR : CLE to RE delay in number of AHB clock cycles, only 4 bits
17 cycles.
19 byte 2 THIZ : number of HCLK clock cycles during which the data bus is
21 Only valid for write transactions. Zero means zero cycles,
22 255 means 255 cycles.
23 byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
25 one cycle, 255 means 256 cycles.
26 byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
28 255 means 256 cycles.
29 byte 5 TSET : number of HCLK clock cycles to assert the address before the
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/linux/drivers/net/ethernet/mellanox/mlx4/
A Den_clock.c44 container_of(tc, struct mlx4_en_dev, cycles); in mlx4_en_read_clock()
141 mdev->cycles.mult = neg_adj ? mult - diff : mult + diff; in mlx4_en_phc_adjfreq()
210 timecounter_init(&mdev->clock, &mdev->cycles, ns); in mlx4_en_phc_settime()
277 memset(&mdev->cycles, 0, sizeof(mdev->cycles)); in mlx4_en_init_timestamp()
278 mdev->cycles.read = mlx4_en_read_clock; in mlx4_en_init_timestamp()
279 mdev->cycles.mask = CLOCKSOURCE_MASK(48); in mlx4_en_init_timestamp()
280 mdev->cycles.shift = freq_to_shift(dev->caps.hca_core_clock); in mlx4_en_init_timestamp()
281 mdev->cycles.mult = in mlx4_en_init_timestamp()
282 clocksource_khz2mult(1000 * dev->caps.hca_core_clock, mdev->cycles.shift); in mlx4_en_init_timestamp()
283 mdev->nominal_c_mult = mdev->cycles.mult; in mlx4_en_init_timestamp()
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/linux/arch/arm64/kvm/
A Dhypercalls.c15 u64 cycles = ~0UL; in kvm_ptp_get_time() local
40 cycles = systime_snapshot.cycles - vcpu_read_sys_reg(vcpu, CNTVOFF_EL2); in kvm_ptp_get_time()
43 cycles = systime_snapshot.cycles; in kvm_ptp_get_time()
57 val[2] = upper_32_bits(cycles); in kvm_ptp_get_time()
58 val[3] = lower_32_bits(cycles); in kvm_ptp_get_time()
/linux/drivers/net/wireless/ath/
A Dhw.c144 u32 cycles, busy, rx, tx; in ath_hw_cycle_counters_update() local
151 cycles = REG_READ(ah, AR_CCCNT); in ath_hw_cycle_counters_update()
166 common->cc_ani.cycles += cycles; in ath_hw_cycle_counters_update()
171 common->cc_survey.cycles += cycles; in ath_hw_cycle_counters_update()
183 listen_time = (cc->cycles - cc->rx_frame - cc->tx_frame) / in ath_hw_get_listen_time()
/linux/drivers/pwm/
A Dpwm-berlin.c96 u64 cycles; in berlin_pwm_config() local
98 cycles = clk_get_rate(bpc->clk); in berlin_pwm_config()
99 cycles *= period_ns; in berlin_pwm_config()
100 do_div(cycles, NSEC_PER_SEC); in berlin_pwm_config()
102 if (cycles > BERLIN_PWM_MAX_TCNT) { in berlin_pwm_config()
104 cycles >>= 12; // Prescaled by 4096 in berlin_pwm_config()
106 if (cycles > BERLIN_PWM_MAX_TCNT) in berlin_pwm_config()
110 period = cycles; in berlin_pwm_config()
111 cycles *= duty_ns; in berlin_pwm_config()
112 do_div(cycles, period_ns); in berlin_pwm_config()
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A Dpwm-atmel.c199 unsigned long long cycles = state->period; in atmel_pwm_calculate_cprd_and_pres() local
203 cycles *= clkrate; in atmel_pwm_calculate_cprd_and_pres()
204 do_div(cycles, NSEC_PER_SEC); in atmel_pwm_calculate_cprd_and_pres()
211 shift = fls(cycles) - atmel_pwm->data->cfg.period_bits; in atmel_pwm_calculate_cprd_and_pres()
218 cycles >>= *pres; in atmel_pwm_calculate_cprd_and_pres()
223 *cprd = cycles; in atmel_pwm_calculate_cprd_and_pres()
232 unsigned long long cycles = state->duty_cycle; in atmel_pwm_calculate_cdty() local
234 cycles *= clkrate; in atmel_pwm_calculate_cdty()
235 do_div(cycles, NSEC_PER_SEC); in atmel_pwm_calculate_cdty()
236 cycles >>= pres; in atmel_pwm_calculate_cdty()
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/linux/drivers/net/ethernet/mellanox/mlxsw/
A Dspectrum_ptp.c64 struct cyclecounter cycles; member
116 u64 cycles = (u64) nsec; in mlxsw_sp1_ptp_ns2cycles() local
118 cycles <<= tc->cc->shift; in mlxsw_sp1_ptp_ns2cycles()
119 cycles = div_u64(cycles, tc->cc->mult); in mlxsw_sp1_ptp_ns2cycles()
121 return cycles; in mlxsw_sp1_ptp_ns2cycles()
128 u64 next_sec, next_sec_in_nsec, cycles; in mlxsw_sp1_ptp_phc_settime() local
140 mlxsw_reg_mtpps_vpin_pack(mtpps_pl, cycles); in mlxsw_sp1_ptp_phc_settime()
200 u64 cycles, nsec; in mlxsw_sp1_ptp_gettimex() local
262 clock->cycles.read = mlxsw_sp1_ptp_read_frc; in mlxsw_sp1_ptp_clock_init()
265 clock->cycles.shift); in mlxsw_sp1_ptp_clock_init()
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/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
A Djedec,lpddr2.yaml69 Active bank a to active bank b in terms of number of clock cycles.
76 Internal WRITE-to-READ command delay in terms of number of clock cycles.
84 cycles. Obtained from device datasheet.
91 cycles. Obtained from device datasheet.
98 of clock cycles. Obtained from device datasheet.
104 Row precharge time (all banks) in terms of number of clock cycles.
111 RAS-to-CAS delay in terms of number of clock cycles. Obtained from
118 WRITE recovery time in terms of number of clock cycles. Obtained from
125 Row active time in terms of number of clock cycles. Obtained from device
133 SELF REFRESH) in terms of number of clock cycles. Obtained from device
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/linux/tools/perf/util/
A Dblock-info.c106 bi->cycles = ch->cycles; in init_block_info()
122 u64 cycles = 0; in block_info__process_sym() local
146 cycles += bi->cycles_aggr / bi->num_aggr; in block_info__process_sym()
158 *block_cycles_aggr += cycles; in block_info__process_sym()
229 static void cycles_string(u64 cycles, char *buf, int size) in cycles_string() argument
231 if (cycles >= 1000000) in cycles_string()
233 else if (cycles >= 1000) in cycles_string()
234 scnprintf(buf, size, "%.1fK", (double)cycles / 1000.0); in cycles_string()
236 scnprintf(buf, size, "%1d", cycles); in cycles_string()
419 block_info__process_sym(he, bh, &block_report->cycles, in process_block_report()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
A Dclock.c142 clock_info->cycles = timer->tc.cycle_last; in mlx5_update_clock_info_page()
143 clock_info->mult = timer->cycles.mult; in mlx5_update_clock_info_page()
258 u64 cycles, ns; in mlx5_ptp_gettimex() local
267 cycles = mlx5_read_time(mdev, sts, false); in mlx5_ptp_gettimex()
445 timer->cycles.mult); in find_target_cycles()
772 timer->cycles.read = read_internal_timer; in mlx5_timecounter_init()
773 timer->cycles.shift = MLX5_CYCLES_SHIFT; in mlx5_timecounter_init()
775 timer->cycles.shift); in mlx5_timecounter_init()
834 info->cycles = timer->tc.cycle_last; in mlx5_init_clock_info()
835 info->mask = timer->cycles.mask; in mlx5_init_clock_info()
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/linux/Documentation/m68k/
A Dbuddha-driver.rst147 497ns Select (7 clock cycles) , IOR/IOW after 172ns (2 clock cycles)
152 639ns Select (9 clock cycles), IOR/IOW after 243ns (3 clock cycles)
155 781ns Select (11 clock cycles), IOR/IOW after 314ns (4 clock cycles)
158 355ns Select (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
161 355ns Select (5 clock cycles), IOR/IOW after 172ns (2 clock cycles)
164 355ns Select (5 clock cycles), IOR/IOW after 243ns (3 clock cycles)
167 1065ns Select (15 clock cycles), IOR/IOW after 314ns (4 clock cycles)
170 355ns Select, (5 clock cycles), IOR/IOW after 101ns (1 clock cycle)
176 781ns select, IOR/IOW after 4 clock cycles (=314ns) aktive.
180 system: Sometimes two more clock cycles are inserted by the
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/linux/lib/vdso/
A Dgettimeofday.c14 u64 vdso_calc_delta(u64 cycles, u64 last, u64 mask, u32 mult) in vdso_calc_delta() argument
16 return ((cycles - last) & mask) * mult; in vdso_calc_delta()
42 static inline bool vdso_cycles_ok(u64 cycles) in vdso_cycles_ok() argument
55 u64 cycles, last, ns; in do_hres_timens() local
73 cycles = __arch_get_hw_counter(vd->clock_mode, vd); in do_hres_timens()
74 if (unlikely(!vdso_cycles_ok(cycles))) in do_hres_timens()
78 ns += vdso_calc_delta(cycles, last, vd->mask, vd->mult); in do_hres_timens()
114 u64 cycles, last, sec, ns; in do_hres() local
144 cycles = __arch_get_hw_counter(vd->clock_mode, vd); in do_hres()
145 if (unlikely(!vdso_cycles_ok(cycles))) in do_hres()
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/linux/arch/xtensa/include/asm/
A Ddelay.h40 unsigned long cycles = (usecs * (ccount_freq >> 15)) >> 5; in __udelay() local
43 while (((unsigned long)get_ccount()) - start < cycles) in __udelay()
61 unsigned long cycles = (nsec * (ccount_freq >> 15)) >> 15; in __ndelay() local
62 __delay(cycles); in __ndelay()
/linux/tools/virtio/ringtest/
A Dmain.h20 static inline void wait_cycles(unsigned long long cycles) in wait_cycles() argument
25 while (__rdtsc() - t < cycles) {} in wait_cycles()
32 static inline void wait_cycles(unsigned long long cycles) in wait_cycles() argument
34 asm volatile("0: brctg %0,0b" : : "d" (cycles)); in wait_cycles()
42 static inline void wait_cycles(unsigned long long cycles) in wait_cycles() argument
/linux/arch/arm/plat-omap/
A Dcounter_32k.c51 static cycles_t cycles; variable
59 last_cycles = cycles; in omap_read_persistent_clock64()
60 cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; in omap_read_persistent_clock64()
62 nsecs = clocksource_cyc2ns(cycles - last_cycles, in omap_read_persistent_clock64()
/linux/tools/perf/tests/attr/
A DREADME50 perf record --group -e cycles,instructions kill (test-record-group)
51 perf record -e '{cycles,instructions}' kill (test-record-group1)
52 perf record -e '{cycles/period=1/,instructions/period=2/}:S' kill (test-record-group2)
57 perf record -c 1 --pfm-events=cycles:period=2 (test-record-pfm-period)
59 perf stat -e cycles kill (test-stat-basic)
64 perf stat --group -e cycles,instructions kill (test-stat-group)
65 perf stat -e '{cycles,instructions}' kill (test-stat-group1)
66 perf stat -i -e cycles kill (test-stat-no-inherit)

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