| /linux/fs/f2fs/ |
| A D | segment.c | 1209 &(dcc->fstrim_list) : &(dcc->wait_list); in __submit_discard_cmd()
1536 dcc->next_pos = 0; in __issue_discard_cmd_orderly()
1673 &(dcc->fstrim_list) : &(dcc->wait_list); in __wait_discard_cmd_range()
1754 if (dcc && dcc->f2fs_issue_discard) { in f2fs_stop_discard_thread()
1805 dcc->discard_wake, in issue_discard_thread()
2166 if (!dcc) in create_discard_cmd_control()
2184 dcc->nr_discards = 0; in create_discard_cmd_control()
2187 dcc->next_pos = 0; in create_discard_cmd_control()
2196 kfree(dcc); in create_discard_cmd_control()
2207 if (!dcc) in destroy_discard_cmd_control()
[all …]
|
| A D | segment.h | 892 struct discard_cmd_control *dcc = SM_I(sbi)->dcc_info; in wake_up_discard_thread() local
899 mutex_lock(&dcc->cmd_lock); in wake_up_discard_thread()
901 if (i + 1 < dcc->discard_granularity) in wake_up_discard_thread()
903 if (!list_empty(&dcc->pend_list[i])) { in wake_up_discard_thread()
908 mutex_unlock(&dcc->cmd_lock); in wake_up_discard_thread()
912 dcc->discard_wake = 1; in wake_up_discard_thread()
913 wake_up_interruptible_all(&dcc->discard_wait_queue); in wake_up_discard_thread()
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_hubp.c | 355 struct dc_plane_dcc_param *dcc) in hubp3_dcc_control_sienna_cichlid() argument
360 PRIMARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
361 PRIMARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
362 PRIMARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c, in hubp3_dcc_control_sienna_cichlid()
363 SECONDARY_SURFACE_DCC_EN, dcc->enable, in hubp3_dcc_control_sienna_cichlid()
364 SECONDARY_SURFACE_DCC_IND_BLK, dcc->dcc_ind_blk, in hubp3_dcc_control_sienna_cichlid()
365 SECONDARY_SURFACE_DCC_IND_BLK_C, dcc->dcc_ind_blk_c); in hubp3_dcc_control_sienna_cichlid()
405 struct dc_plane_dcc_param *dcc, in hubp3_program_surface_config() argument
411 hubp3_dcc_control_sienna_cichlid(hubp, dcc); in hubp3_program_surface_config()
413 hubp2_program_size(hubp, format, plane_size, dcc); in hubp3_program_surface_config()
|
| A D | dcn30_hubp.h | 270 struct dc_plane_dcc_param *dcc,
285 struct dc_plane_dcc_param *dcc);
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_hubp.c | 48 struct dc_plane_dcc_param *dcc, in hubp201_program_surface_config() argument
52 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp201_program_surface_config()
54 hubp1_program_size(hubp, format, plane_size, dcc); in hubp201_program_surface_config()
|
| /linux/drivers/bus/ |
| A D | vexpress-config.c | 108 u32 *position, u32 *dcc) in vexpress_config_get_topo() argument
116 vexpress_config_find_prop(node, "arm,vexpress,dcc", dcc); in vexpress_config_get_topo()
257 u32 site, position, dcc; in vexpress_syscfg_regmap_init() local
261 &position, &dcc); in vexpress_syscfg_regmap_init()
301 func, site, position, dcc, in vexpress_syscfg_regmap_init()
304 func->template[i] = SYS_CFGCTRL_DCC(dcc); in vexpress_syscfg_regmap_init()
|
| /linux/arch/arm64/boot/dts/xilinx/ |
| A D | zynqmp-zc1275-revA.dts | 22 serial1 = &dcc;
37 &dcc {
|
| A D | zynqmp-zc1254-revA.dts | 22 serial1 = &dcc;
37 &dcc {
|
| A D | zynqmp-zc1232-revA.dts | 21 serial1 = &dcc;
36 &dcc {
|
| A D | zynqmp-zcu104-revA.dts | 30 serial2 = &dcc;
70 &dcc {
|
| A D | zynqmp-zcu104-revC.dts | 30 serial2 = &dcc;
75 &dcc {
|
| A D | zynqmp-zcu100-revC.dts | 30 serial2 = &dcc;
129 &dcc {
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hubp.c | 167 struct dc_plane_dcc_param *dcc) in hubp1_program_size() argument
180 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
182 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp1_program_size()
185 meta_pitch = dcc->meta_pitch - 1; in hubp1_program_size()
190 if (!dcc->enable) { in hubp1_program_size()
541 struct dc_plane_dcc_param *dcc, in hubp1_program_surface_config() argument
545 hubp1_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp1_program_surface_config()
547 hubp1_program_size(hubp, format, plane_size, dcc); in hubp1_program_surface_config()
|
| /linux/drivers/gpu/drm/i915/gt/ |
| A D | intel_ggtt_fencing.c | 662 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle() local
673 switch (dcc & DCC_ADDRESSING_MODE_MASK) { in detect_bit_6_swizzle()
680 if (dcc & DCC_CHANNEL_XOR_DISABLE) { in detect_bit_6_swizzle()
687 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) { in detect_bit_6_swizzle()
706 if (dcc == 0xffffffff) { in detect_bit_6_swizzle()
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_hubp.c | 331 struct dc_plane_dcc_param *dcc) in hubp2_program_size() argument
349 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
351 meta_pitch_c = dcc->meta_pitch_c - 1; in hubp2_program_size()
354 meta_pitch = dcc->meta_pitch - 1; in hubp2_program_size()
359 if (!dcc->enable) { in hubp2_program_size()
541 struct dc_plane_dcc_param *dcc, in hubp2_program_surface_config() argument
547 hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks); in hubp2_program_surface_config()
549 hubp2_program_size(hubp, format, plane_size, dcc); in hubp2_program_surface_config()
|
| A D | dcn20_hubp.h | 309 struct dc_plane_dcc_param *dcc);
326 struct dc_plane_dcc_param *dcc,
|
| /linux/arch/arm/boot/dts/ |
| A D | vexpress-v2p-ca5s.dts | 143 dcc {
201 temp-dcc {
|
| A D | vexpress-v2p-ca15-tc1.dts | 141 dcc {
217 temp-dcc {
|
| A D | vexpress-v2p-ca15_a7.dts | 252 dcc {
373 temp-dcc {
|
| /linux/drivers/tty/hvc/ |
| A D | hvc_dcc.c | 41 EARLYCON_DECLARE(dcc, dcc_early_console_setup);
|
| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | mem_input.h | 159 struct dc_plane_dcc_param *dcc,
|
| A D | hubp.h | 135 struct dc_plane_dcc_param *dcc,
|
| /linux/fs/ext4/ |
| A D | balloc.c | 574 struct percpu_counter *dcc = &sbi->s_dirtyclusters_counter; in ext4_has_free_clusters() local
577 dirty_clusters = percpu_counter_read_positive(dcc); in ext4_has_free_clusters()
590 dirty_clusters = percpu_counter_sum_positive(dcc); in ext4_has_free_clusters()
|
| /linux/arch/arm64/boot/dts/arm/ |
| A D | vexpress-v2f-1xv7-ca53x2.dts | 108 dcc {
|
| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm.c | 4769 if (!dcc->enable) in validate_dcc()
4792 if (dcc->independent_64b_blks == 0 && in validate_dcc()
5215 struct dc_plane_dcc_param *dcc, in fill_gfx9_plane_attributes_from_modifiers() argument
5230 dcc->enable = 1; in fill_gfx9_plane_attributes_from_modifiers()
5231 dcc->meta_pitch = afb->base.pitches[1]; in fill_gfx9_plane_attributes_from_modifiers()
5239 dcc->dcc_ind_blk = hubp_ind_block_64b; in fill_gfx9_plane_attributes_from_modifiers()
5244 dcc->dcc_ind_blk = hubp_ind_block_64b; in fill_gfx9_plane_attributes_from_modifiers()
5268 struct dc_plane_dcc_param *dcc, in fill_plane_buffer_attributes() argument
5278 memset(dcc, 0, sizeof(*dcc)); in fill_plane_buffer_attributes()
5330 tiling_info, dcc, in fill_plane_buffer_attributes()
[all …]
|