| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_dccg.c | 160 struct dccg *dccg, in dccg31_set_dpstreamclk() argument
171 struct dccg *dccg, in dccg31_enable_symclk32_se() argument
220 struct dccg *dccg, in dccg31_disable_symclk32_se() argument
266 struct dccg *dccg, in dccg31_enable_symclk32_le() argument
299 struct dccg *dccg, in dccg31_disable_symclk32_le() argument
399 struct dccg *dccg, in dccg31_set_physymclk() argument
466 struct dccg *dccg, in dccg31_set_dtbclk_dto() argument
538 struct dccg *dccg, in dccg31_set_audio_dtbclk_dto() argument
573 static void dccg31_get_dccg_ref_freq(struct dccg *dccg, in dccg31_get_dccg_ref_freq() argument
586 struct dccg *dccg, in dccg31_set_dispclk_change_mode() argument
[all …]
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| A D | dcn31_dccg.h | 150 struct dccg *dccg31_create(
156 void dccg31_init(struct dccg *dccg);
159 struct dccg *dccg,
164 struct dccg *dccg,
169 struct dccg *dccg,
173 struct dccg *dccg,
178 struct dccg *dccg,
182 struct dccg *dccg,
188 struct dccg *dccg,
192 struct dccg *dccg,
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| A D | dcn31_hwseq.c | 147 if (res_pool->dccg->funcs->dccg_init) in dcn31_init_hw()
148 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
157 if (res_pool->dccg && res_pool->hubbub) { in dcn31_init_hw()
159 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn31_init_hw()
323 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn31_dsc_pg_control()
325 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn31_dsc_pg_control()
326 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn31_dsc_pg_control()
366 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) in dcn31_dsc_pg_control()
367 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn31_dsc_pg_control()
368 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn31_dsc_pg_control()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | dccg.h | 84 struct dccg *dccg,
89 struct dccg *dccg,
94 struct dccg *dccg,
98 struct dccg *dccg,
103 struct dccg *dccg,
107 struct dccg *dccg,
113 struct dccg *dccg,
120 struct dccg *dccg,
124 struct dccg *dccg,
128 struct dccg *dccg,
[all …]
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| A D | clk_mgr.h | 285 struct dccg;
287 …clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_dccg.c | 32 #define TO_DCN_DCCG(dccg)\ argument
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
77 void dccg2_get_dccg_ref_freq(struct dccg *dccg, in dccg2_get_dccg_ref_freq() argument
99 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, in dccg2_set_fifo_errdet_ovr_en() argument
108 void dccg2_otg_add_pixel(struct dccg *dccg, in dccg2_otg_add_pixel() argument
120 void dccg2_otg_drop_pixel(struct dccg *dccg, in dccg2_otg_drop_pixel() argument
132 void dccg2_init(struct dccg *dccg) in dccg2_init() argument
152 struct dccg *base; in dccg2_create()
170 void dcn_dccg_destroy(struct dccg **dccg) in dcn_dccg_destroy() argument
[all …]
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| A D | dcn20_dccg.h | 243 struct dccg base;
249 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
251 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
255 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
257 void dccg2_otg_add_pixel(struct dccg *dccg,
259 void dccg2_otg_drop_pixel(struct dccg *dccg,
263 void dccg2_init(struct dccg *dccg);
265 struct dccg *dccg2_create(
271 void dcn_dccg_destroy(struct dccg **dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
109 struct dccg *dccg21_create( in dccg21_create()
116 struct dccg *base; in dccg21_create()
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| A D | dcn21_dccg.h | 29 struct dccg *dccg21_create(
35 void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_dccg.c | 31 #define TO_DCN_DCCG(dccg)\ argument
32 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg201_update_dpp_dto() argument
61 struct dccg *dccg201_create( in dccg201_create()
68 struct dccg *base; in dccg201_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 148 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
162 dccg, in dcn20_update_clocks_update_dentist()
165 dccg->funcs->otg_drop_pixel( in dcn20_update_clocks_update_dentist()
166 dccg, in dcn20_update_clocks_update_dentist()
169 dccg, in dcn20_update_clocks_update_dentist()
178 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
192 dccg->funcs->set_fifo_errdet_ovr_en(dccg, true); in dcn20_update_clocks_update_dentist()
194 dccg->funcs->otg_add_pixel(dccg, in dcn20_update_clocks_update_dentist()
196 dccg->funcs->set_fifo_errdet_ovr_en(dccg, false); in dcn20_update_clocks_update_dentist()
534 struct dccg *dccg) in dcn20_clk_mgr_construct() argument
[all …]
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| A D | dcn20_clk_mgr.h | 29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
55 struct dccg *dccg3_create( in dccg3_create()
62 struct dccg *base; in dccg3_create()
80 struct dccg *dccg30_create( in dccg30_create()
87 struct dccg *base; in dccg30_create()
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| A D | dcn30_dccg.h | 69 struct dccg *dccg3_create(
75 struct dccg *dccg30_create(
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| A D | clk_mgr.c | 138 … clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
224 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
229 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
251 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
255 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
259 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
263 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
266 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
277 vg_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
289 dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| A D | dcn301_dccg.c | 30 #define TO_DCN_DCCG(dccg)\ argument
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
54 struct dccg *dccg301_create( in dccg301_create()
61 struct dccg *base; in dccg301_create()
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| A D | dcn301_dccg.h | 53 struct dccg *dccg301_create(
59 struct dccg *dccg301_create(
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_link_hwss.c | 800 dc->res_pool->dccg->funcs->set_physymclk(
801 dc->res_pool->dccg,
808 dc->res_pool->dccg,
825 dc->res_pool->dccg,
829 dc->res_pool->dccg,
856 dc->res_pool->dccg,
862 dc->res_pool->dccg,
867 dc->res_pool->dccg,
874 dc->res_pool->dccg,
880 dc->res_pool->dccg,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| A D | dcn201_clk_mgr.h | 32 struct dccg *dccg);
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| A D | dcn201_clk_mgr.c | 217 struct dccg *dccg) in dcn201_clk_mgr_construct() argument
227 clk_mgr->dccg = dccg; in dcn201_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr.h | 39 struct dccg *dccg);
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| A D | rn_clk_mgr.c | 105 clk_mgr->dccg->ref_dppclk = ref_dpp_clk; in rn_update_clocks_update_dpp_dto()
116 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in rn_update_clocks_update_dpp_dto()
119 clk_mgr->dccg->funcs->update_dpp_dto( in rn_update_clocks_update_dpp_dto()
120 clk_mgr->dccg, dpp_inst, dppclk_khz); in rn_update_clocks_update_dpp_dto()
939 struct dccg *dccg) in rn_clk_mgr_construct() argument
955 clk_mgr->dccg = dccg; in rn_clk_mgr_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_clk_mgr.h | 34 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | vg_clk_mgr.h | 45 struct dccg *dccg);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.h | 45 struct dccg *dccg);
|