| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| A D | dcn301_fpu.c | 118 .dcfclk_mhz = 400.0,
130 .dcfclk_mhz = 400.0,
142 .dcfclk_mhz = 608.0,
154 .dcfclk_mhz = 676.0,
166 .dcfclk_mhz = 810.0,
229 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
268 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn301_update_bw_bounding_box()
275 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn301_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn303/ |
| A D | dcn303_resource.c | 1217 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn303_update_bw_bounding_box() local
1240 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn303_update_bw_bounding_box()
1241 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn303_update_bw_bounding_box()
1250 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz; in dcn303_update_bw_bounding_box()
1298 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_update_bw_bounding_box()
1302 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_update_bw_bounding_box()
1312 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn303_update_bw_bounding_box()
1318 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn303_update_bw_bounding_box()
1325 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn303_update_bw_bounding_box()
1326 dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i]; in dcn303_update_bw_bounding_box()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| A D | dcn21_resource.c | 170 .dcfclk_mhz = 400.0,
181 .dcfclk_mhz = 464.52,
192 .dcfclk_mhz = 514.29,
203 .dcfclk_mhz = 576.00,
214 .dcfclk_mhz = 626.09,
225 .dcfclk_mhz = 685.71,
236 .dcfclk_mhz = 757.89,
247 .dcfclk_mhz = 847.06,
1047 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
1569 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz; in construct_low_pstate_lvl()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn302/ |
| A D | dcn302_resource.c | 1287 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn302_update_bw_bounding_box() local
1310 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz) in dcn302_update_bw_bounding_box()
1311 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in dcn302_update_bw_bounding_box()
1320 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz; in dcn302_update_bw_bounding_box()
1351 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz; in dcn302_update_bw_bounding_box()
1371 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_update_bw_bounding_box()
1375 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_update_bw_bounding_box()
1384 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn302_update_bw_bounding_box()
1390 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn302_update_bw_bounding_box()
1397 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn302_update_bw_bounding_box()
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | vg_clk_mgr.c | 421 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in vg_build_watermark_ranges()
424 bw_params->clk_table.entries[i].dcfclk_mhz; in vg_build_watermark_ranges()
509 .dcfclk_mhz = 400,
516 .dcfclk_mhz = 483,
523 .dcfclk_mhz = 602,
530 .dcfclk_mhz = 738,
664 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfP… in vg_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr.c | 490 …der_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in build_watermark_ranges()
492 …ges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz; in build_watermark_ranges()
593 .dcfclk_mhz = 400,
600 .dcfclk_mhz = 483,
607 .dcfclk_mhz = 602,
614 .dcfclk_mhz = 738,
903 …bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FCl… in rn_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 237 .dcfclk_mhz = 560.0,
248 .dcfclk_mhz = 694.0,
259 .dcfclk_mhz = 875.0,
270 .dcfclk_mhz = 1000.0,
281 .dcfclk_mhz = 1200.0,
293 .dcfclk_mhz = 1200.0,
348 .dcfclk_mhz = 560.0,
359 .dcfclk_mhz = 694.0,
370 .dcfclk_mhz = 875.0,
381 .dcfclk_mhz = 1000.0,
[all …]
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| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| A D | dcn30_resource.c | 2140 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg_fp()
2150 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn30_calculate_wm_and_dlg_fp()
2166 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn30_calculate_wm_and_dlg_fp()
2388 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; in dcn30_update_bw_bounding_box() local
2421 max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_update_bw_bounding_box()
2474 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2478 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2487 dcfclk_mhz[num_states] = dcfclk_sta_targets[i]; in dcn30_update_bw_bounding_box()
2493 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j]; in dcn30_update_bw_bounding_box()
2500 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i]; in dcn30_update_bw_bounding_box()
[all …]
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_socbb.h | 29 uint32_t dcfclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| A D | display_mode_structs.h | 60 double dcfclk_mhz; member
377 double dcfclk_mhz; member
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| A D | display_mode_lib.c | 257 dml_print("DML PARAMS: dcfclk_mhz = %3.2f\n", clks_cfg->dcfclk_mhz); in dml_log_pipe_params()
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| A D | display_mode_vba.c | 264 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
279 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
886 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn201/ |
| A D | dcn201_resource.c | 144 .dcfclk_mhz = 1000.0,
155 .dcfclk_mhz = 1000.0,
166 .dcfclk_mhz = 1000.0,
177 .dcfclk_mhz = 1000.0,
188 .dcfclk_mhz = 1000.0,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.c | 433 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1; in dcn31_build_watermark_ranges()
436 bw_params->clk_table.entries[i].dcfclk_mhz; in dcn31_build_watermark_ranges()
597 …bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClo… in dcn31_clk_mgr_helper_populate_bw_params()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | clk_mgr.h | 86 unsigned int dcfclk_mhz; member
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| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| A D | dcn31_resource.c | 1876 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
1886 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1904 pipes[0].clks_cfg.dcfclk_mhz = dcfclk; in dcn31_calculate_wm_and_dlg_fp()
2084 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) { in dcn31_update_bw_bounding_box()
2093 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn31_update_bw_bounding_box()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_clk_mgr.c | 185 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz, in dcn3_init_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/calcs/ |
| A D | dcn_calcs.c | 494 input->clks_cfg.dcfclk_mhz = v->dcfclk; in dcn_bw_calc_rq_dlg_ttu()
|