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Searched refs:dcn3_01_soc (Results 1 – 3 of 3) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c111 struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = { variable
262 dcn3_01_soc.num_chans = bw_params->num_channels; in dcn301_update_bw_bounding_box()
267 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) { in dcn301_update_bw_bounding_box()
281 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz; in dcn301_update_bw_bounding_box()
283 clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz; in dcn301_update_bw_bounding_box()
290 dcn3_01_soc.clock_limits[i] = clock_limits[i]; in dcn301_update_bw_bounding_box()
293 dcn3_01_soc.num_states = clk_table->num_entries; in dcn301_update_bw_bounding_box()
295 …dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states… in dcn301_update_bw_bounding_box()
296 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states; in dcn301_update_bw_bounding_box()
303 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); in dcn301_update_bw_bounding_box()
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/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_resource.h36 extern struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc;
A Ddcn301_resource.c1320 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc; in init_soc_bounding_box()
1549 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); in dcn301_resource_construct()
1560 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); in dcn301_resource_construct()

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