Searched refs:deferred_reg_writes (Results 1 – 4 of 4) sorted by relevance
497 if (dpp_base->deferred_reg_writes.bits.disable_dscl) { in dpp3_deferred_update()499 dpp_base->deferred_reg_writes.bits.disable_dscl = false; in dpp3_deferred_update()502 if (dpp_base->deferred_reg_writes.bits.disable_gamcor) { in dpp3_deferred_update()508 dpp_base->deferred_reg_writes.bits.disable_gamcor = false; in dpp3_deferred_update()511 if (dpp_base->deferred_reg_writes.bits.disable_blnd_lut) { in dpp3_deferred_update()520 if (dpp_base->deferred_reg_writes.bits.disable_3dlut) { in dpp3_deferred_update()526 dpp_base->deferred_reg_writes.bits.disable_3dlut = false; in dpp3_deferred_update()529 if (dpp_base->deferred_reg_writes.bits.disable_shaper) { in dpp3_deferred_update()535 dpp_base->deferred_reg_writes.bits.disable_shaper = false; in dpp3_deferred_update()571 dpp_base->deferred_reg_writes.bits.disable_3dlut = true; in dpp3_power_on_hdr3dlut()[all …]
144 dpp_base->deferred_reg_writes.bits.disable_gamcor = true; in dpp3_power_on_gamcor_lut()
57 union defer_reg_writes deferred_reg_writes; member
214 dpp->base.deferred_reg_writes.bits.disable_dscl = true; in dpp1_power_on_dscl()
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