1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Marvell Fibre Channel HBA Driver
4  * Copyright (c)  2021    Marvell
5  */
6 #ifndef __QLA_EDIF_H
7 #define __QLA_EDIF_H
8 
9 struct qla_scsi_host;
10 #define EDIF_APP_ID 0x73730001
11 
12 #define EDIF_MAX_INDEX	2048
13 struct edif_sa_ctl {
14 	struct list_head next;
15 	uint16_t	del_index;
16 	uint16_t	index;
17 	uint16_t	slot;
18 	uint16_t	flags;
19 #define	EDIF_SA_CTL_FLG_REPL		BIT_0
20 #define	EDIF_SA_CTL_FLG_DEL		BIT_1
21 #define EDIF_SA_CTL_FLG_CLEANUP_DEL BIT_4
22 	// Invalidate Index bit and mirrors QLA_SA_UPDATE_FLAGS_DELETE
23 	unsigned long   state;
24 #define EDIF_SA_CTL_USED	1	/* Active Sa update  */
25 #define EDIF_SA_CTL_PEND	2	/* Waiting for slot */
26 #define EDIF_SA_CTL_REPL	3	/* Active Replace and Delete */
27 #define EDIF_SA_CTL_DEL		4	/* Delete Pending */
28 	struct fc_port	*fcport;
29 	struct bsg_job *bsg_job;
30 	struct qla_sa_update_frame sa_frame;
31 };
32 
33 enum enode_flags_t {
34 	ENODE_ACTIVE = 0x1,
35 };
36 
37 struct pur_core {
38 	enum enode_flags_t	enode_flags;
39 	spinlock_t		pur_lock;
40 	struct  list_head	head;
41 };
42 
43 enum db_flags_t {
44 	EDB_ACTIVE = BIT_0,
45 };
46 
47 #define DBELL_ACTIVE(_v) (_v->e_dbell.db_flags & EDB_ACTIVE)
48 #define DBELL_INACTIVE(_v) (!(_v->e_dbell.db_flags & EDB_ACTIVE))
49 
50 struct edif_dbell {
51 	enum db_flags_t		db_flags;
52 	spinlock_t		db_lock;
53 	struct  list_head	head;
54 	struct	completion	dbell;
55 };
56 
57 #define SA_UPDATE_IOCB_TYPE            0x71    /* Security Association Update IOCB entry */
58 struct sa_update_28xx {
59 	uint8_t entry_type;             /* Entry type. */
60 	uint8_t entry_count;            /* Entry count. */
61 	uint8_t sys_define;             /* System Defined. */
62 	uint8_t entry_status;           /* Entry Status. */
63 
64 	uint32_t handle;                /* IOCB System handle. */
65 
66 	union {
67 		__le16 nport_handle;  /* in: N_PORT handle. */
68 		__le16 comp_sts;              /* out: completion status */
69 #define CS_PORT_EDIF_UNAVAIL	0x28
70 #define CS_PORT_EDIF_LOGOUT	0x29
71 #define CS_PORT_EDIF_SUPP_NOT_RDY 0x64
72 #define CS_PORT_EDIF_INV_REQ      0x66
73 	} u;
74 	uint8_t vp_index;
75 	uint8_t reserved_1;
76 	uint8_t port_id[3];
77 	uint8_t flags;
78 #define SA_FLAG_INVALIDATE BIT_0
79 #define SA_FLAG_TX	   BIT_1 // 1=tx, 0=rx
80 
81 	uint8_t sa_key[32];     /* 256 bit key */
82 	__le32 salt;
83 	__le32 spi;
84 	uint8_t sa_control;
85 #define SA_CNTL_ENC_FCSP        (1 << 3)
86 #define SA_CNTL_ENC_OPD         (2 << 3)
87 #define SA_CNTL_ENC_MSK         (3 << 3)  // mask bits 4,3
88 #define SA_CNTL_AES_GMAC	(1 << 2)
89 #define SA_CNTL_KEY256          (2 << 0)
90 #define SA_CNTL_KEY128          0
91 
92 	uint8_t reserved_2;
93 	__le16 sa_index;   // reserve: bit 11-15
94 	__le16 old_sa_info;
95 	__le16 new_sa_info;
96 };
97 
98 #define        NUM_ENTRIES     256
99 #define        PUR_GET         1
100 
101 struct dinfo {
102 	int		nodecnt;
103 	int		lstate;
104 };
105 
106 struct pur_ninfo {
107 	port_id_t       pur_sid;
108 	port_id_t	pur_did;
109 	uint8_t		vp_idx;
110 	short           pur_bytes_rcvd;
111 	unsigned short  pur_nphdl;
112 	unsigned int    pur_rx_xchg_address;
113 };
114 
115 struct purexevent {
116 	struct  pur_ninfo	pur_info;
117 	unsigned char		*msgp;
118 	u32			msgp_len;
119 };
120 
121 #define	N_UNDEF		0
122 #define	N_PUREX		1
123 struct enode {
124 	struct list_head	list;
125 	struct dinfo		dinfo;
126 	uint32_t		ntype;
127 	union {
128 		struct purexevent	purexinfo;
129 	} u;
130 };
131 
132 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
133 
134 #define EDIF_SESSION_DOWN(_s) \
135 	(qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
136 	 _s->disc_state == DSC_DELETED || \
137 	 !_s->edif.app_sess_online))
138 
139 #define EDIF_NEGOTIATION_PENDING(_fcport) \
140 	(DBELL_ACTIVE(_fcport->vha) && \
141 	 (_fcport->disc_state == DSC_LOGIN_AUTH_PEND))
142 
143 #endif	/* __QLA_EDIF_H */
144