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Searched refs:dev_priv (Results 1 – 25 of 280) sorted by relevance

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/linux/drivers/gpu/drm/i915/
A Dintel_pch.c16 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5); in intel_pch_type()
32 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
34 IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
39 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
41 !IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); in intel_pch_type()
46 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)); in intel_pch_type()
48 IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)); in intel_pch_type()
56 !IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv)); in intel_pch_type()
112 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in intel_pch_type()
116 drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv)); in intel_pch_type()
[all …]
A Di915_irq.c187 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || in intel_hpd_init_pins()
197 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in intel_hpd_init_pins()
207 (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) in intel_hpd_init_pins()
214 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) in intel_hpd_init_pins()
216 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv)) in intel_hpd_init_pins()
597 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); in i915_has_asle()
890 IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 || in i915_get_crtc_scanoutpos()
1404 if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) in i9xx_pipe_crc_irq_handler()
3008 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv)) in ibx_irq_reset()
3778 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen8_de_irq_postinstall()
[all …]
A Di915_drv.c160 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_setup_mchbar()
165 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { in intel_setup_mchbar()
183 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { in intel_setup_mchbar()
198 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) { in intel_teardown_mchbar()
276 pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6; in intel_detect_preproduction_hw()
277 pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA; in intel_detect_preproduction_hw()
278 pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1; in intel_detect_preproduction_hw()
280 pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7; in intel_detect_preproduction_hw()
316 intel_uncore_init_early(&dev_priv->uncore, dev_priv); in i915_driver_early_probe()
347 intel_gt_init_early(&dev_priv->gt, dev_priv); in i915_driver_early_probe()
[all …]
A Di915_drv.h1322 #define INTEL_INFO(dev_priv) (&(dev_priv)->__info) argument
1324 #define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps) argument
1438 #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) argument
1607 #define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv)) argument
1608 #define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv)) argument
1634 #define HAS_WT(dev_priv) HAS_EDRAM(dev_priv) argument
1661 #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) argument
1668 (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
1685 #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7) argument
1687 #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) argument
[all …]
A Di915_suspend.c41 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { in intel_save_swf()
43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
66 if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { in intel_restore_swf()
95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); in i915_save_display()
[all …]
A Dintel_pch.h64 #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) argument
65 #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) argument
66 #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) argument
67 #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) argument
68 #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) argument
69 #define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP) argument
70 #define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC) argument
71 #define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP) argument
72 #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) argument
73 #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) argument
[all …]
/linux/drivers/gpu/drm/via/
A Dvia_dma.c94 (dev_priv->dma_high + hw_addr - dev_priv->dma_low) : in via_cmdbuf_space()
109 (dev_priv->dma_wrap + dev_priv->dma_low - hw_addr)); in via_cmdbuf_lag()
158 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); in via_check_dma()
183 if (!dev_priv || !dev_priv->mmio) { in via_initialize()
218 dev_priv->ring.virtual_start = dev_priv->ring.map.handle; in via_initialize()
220 dev_priv->dma_ptr = dev_priv->ring.virtual_start; in via_initialize()
398 return (uint32_t *) (dev_priv->dma_ptr + dev_priv->dma_low); in via_get_dma()
425 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; in via_hook_segment()
427 dev_priv->last_pause_ptr = via_get_dma(dev_priv) - 1; in via_hook_segment()
563 dev_priv->dma_offset + (uint32_t) dev_priv->agpAddr + 4; in via_cmdbuf_start()
[all …]
A Dvia_irq.c119 dev_priv->nsec_per_vblank = in via_driver_irq_handler()
121 dev_priv->last_vblank) >> 4; in via_driver_irq_handler()
161 if (dev_priv) { in viadrv_acknowledge_irqs()
165 dev_priv->irq_pending_mask); in viadrv_acknowledge_irqs()
216 if (!dev_priv) { in via_driver_irq_wait()
234 masks = dev_priv->irq_masks; in via_driver_irq_wait()
265 if (dev_priv) { in via_driver_irq_preinstall()
266 cur_irq = dev_priv->via_irqs; in via_driver_irq_preinstall()
312 if (!dev_priv) in via_driver_irq_postinstall()
317 | dev_priv->irq_enable_mask); in via_driver_irq_postinstall()
[all …]
/linux/drivers/gpu/drm/savage/
A Dsavage_bci.c224 dev_priv->head.next = &dev_priv->tail; in savage_freelist_init()
229 dev_priv->tail.prev = &dev_priv->head; in savage_freelist_init()
308 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size / in savage_dma_init()
350 if (dev_priv->cmd_dma == &dev_priv->fake_dma) in savage_dma_wait()
365 if (dev_priv->wait_evnt(dev_priv, in savage_dma_wait()
394 dev_priv->dma_flush(dev_priv); in savage_dma_alloc()
398 dev_priv->dma_pages[i].age = dev_priv->last_dma_age; in savage_dma_alloc()
423 savage_dma_wait(dev_priv, dev_priv->current_dma_page); in savage_dma_alloc()
801 dev_priv->cmd_dma = &dev_priv->fake_dma; in savage_do_init_bci()
892 if (dev_priv->cmd_dma == &dev_priv->fake_dma) { in savage_do_cleanup_bci()
[all …]
/linux/drivers/gpu/drm/vmwgfx/
A Dvmwgfx_drv.c441 dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE); in vmw_device_init()
452 dev_priv->fifo = vmw_fifo_create(dev_priv); in vmw_device_init()
461 dev_priv->last_read_seqno = vmw_fence_read(dev_priv); in vmw_device_init()
533 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); in vmw_request_device()
829 dev_priv->drm.dev_private = dev_priv; in vmw_driver_load()
894 dev_priv->memory_size -= dev_priv->vram_size; in vmw_driver_load()
934 dev_priv->texture_max_width = vmw_read(dev_priv, in vmw_driver_load()
938 dev_priv->texture_max_height = vmw_read(dev_priv, in vmw_driver_load()
943 dev_priv->max_primary_mem = dev_priv->vram_size; in vmw_driver_load()
953 dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages); in vmw_driver_load()
[all …]
A Dvmwgfx_irq.c54 vmw_fences_update(dev_priv->fman); in vmw_thread_fn()
96 wake_up_all(&dev_priv->fifo_queue); in vmw_irq_handler()
123 dev_priv->last_read_seqno = seqno; in vmw_update_seqno()
124 vmw_fences_update(dev_priv->fman); in vmw_update_seqno()
136 vmw_update_seqno(dev_priv); in vmw_seqno_passed()
141 vmw_fifo_idle(dev_priv, seqno)) in vmw_seqno_passed()
180 if (dev_priv->cman) { in vmw_fallback_wait()
238 dev_priv->irq_mask |= flag; in vmw_generic_waiter_add()
239 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_generic_waiter_add()
249 dev_priv->irq_mask &= ~flag; in vmw_generic_waiter_remove()
[all …]
A Dvmwgfx_cmd.c46 if (!dev_priv->has_mob) in vmw_supports_3d()
102 if (!dev_priv->fifo_mem) in vmw_fifo_create()
130 vmw_fifo_mem_write(dev_priv, SVGA_FIFO_MAX, dev_priv->fifo_mem_size); in vmw_fifo_create()
143 drm_info(&dev_priv->drm, in vmw_fifo_create()
176 dev_priv->fifo = NULL; in vmw_fifo_destroy()
241 (dev_priv->fifo_queue, in vmw_fifo_wait()
362 if (dev_priv->cman) in vmw_cmd_ctx_reserve()
466 if (dev_priv->cman) in vmw_cmd_commit()
481 if (dev_priv->cman) in vmw_cmd_commit_flush()
498 if (dev_priv->cman) in vmw_cmd_flush()
[all …]
/linux/drivers/gpu/drm/i915/display/
A Dintel_fbc.c503 if (IS_BROADWELL(dev_priv) || (DISPLAY_VER(dev_priv) == 9 && in intel_fbc_stolen_end()
566 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) { in intel_fbc_alloc_cfb()
658 if (DISPLAY_VER(dev_priv) == 2 || DISPLAY_VER(dev_priv) == 3) in stride_is_valid()
665 if ((DISPLAY_VER(dev_priv) == 9 || IS_GEMINILAKE(dev_priv)) && in stride_is_valid()
702 else if (DISPLAY_VER(dev_priv) <= 4 && !IS_G4X(dev_priv) && in rotation_is_valid()
724 } else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) { in intel_fbc_hw_tracking_covers_screen()
727 } else if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5) { in intel_fbc_hw_tracking_covers_screen()
772 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) in intel_fbc_update_state_cache()
943 if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) && in intel_fbc_can_activate()
1533 if (IS_BROADWELL(dev_priv) || DISPLAY_VER(dev_priv) >= 9) in intel_sanitize_fbc_option()
[all …]
A Dintel_cdclk.c66 dev_priv->cdclk_funcs->get_cdclk(dev_priv, cdclk_config); in intel_cdclk_get_cdclk()
79 dev_priv->cdclk_funcs->set_cdclk(dev_priv, cdclk_config, pipe); in intel_cdclk_set_cdclk()
541 if (dev_priv->cdclk.hw.cdclk >= dev_priv->czclk_freq) { in vlv_program_pfi_credits()
1686 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in bxt_set_cdclk()
1774 if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) && in bxt_sanitize_cdclk()
2080 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_pixel_rate_to_cdclk()
2641 IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) in intel_compute_max_dotclk()
2718 dev_priv->max_cdclk_freq = dev_priv->cdclk.hw.cdclk; in intel_update_max_cdclk()
2738 intel_cdclk_get_cdclk(dev_priv, &dev_priv->cdclk.hw); in intel_update_cdclk()
2746 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_update_cdclk()
[all …]
A Dintel_fifo_underrun.c63 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
81 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
122 intel_de_write(dev_priv, reg, in i9xx_set_fifo_underrun_reporting()
181 drm_err(&dev_priv->drm, in ivb_set_fifo_underrun_reporting()
271 drm_err(&dev_priv->drm, in cpt_set_fifo_underrun_reporting()
290 if (HAS_GMCH(dev_priv)) in __intel_set_cpu_fifo_underrun_reporting()
292 else if (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv)) in __intel_set_cpu_fifo_underrun_reporting()
369 if (HAS_PCH_IBX(dev_priv)) in intel_set_pch_fifo_underrun_reporting()
402 if (HAS_GMCH(dev_priv) && in intel_cpu_fifo_underrun_irq_handler()
479 if (HAS_GMCH(dev_priv)) in intel_check_cpu_fifo_underruns()
[all …]
A Dintel_fdi.c18 if (HAS_DDI(dev_priv)) { in assert_fdi_tx()
129 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
133 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
139 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { in ilk_check_fdi_lanes()
141 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
168 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
176 drm_dbg_kms(&dev_priv->drm, in ilk_check_fdi_lanes()
283 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
286 drm_WARN_ON(&dev_priv->drm, in cpt_set_fdi_bc_bifurcation()
360 if (IS_IVYBRIDGE(dev_priv)) in intel_fdi_normal_train()
[all …]
A Dintel_drrs.c104 drm_dbg_kms(&dev_priv->drm, in intel_drrs_set_state()
118 drm_dbg_kms(&dev_priv->drm, in intel_drrs_set_state()
123 if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { in intel_drrs_set_state()
133 drm_err(&dev_priv->drm, in intel_drrs_set_state()
142 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_drrs_set_state()
147 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) in intel_drrs_set_state()
193 if (dev_priv->drrs.dp) { in intel_drrs_enable()
211 dev_priv->drrs.dp = NULL; in intel_drrs_disable_locked()
229 if (!dev_priv->drrs.dp) { in intel_drrs_disable()
431 dev_priv->drrs.type = dev_priv->vbt.drrs_type; in intel_drrs_init()
[all …]
A Dintel_gmbus.c288 struct drm_i915_private *dev_priv = bus->dev_priv; in intel_gpio_pre_xfer() local
307 struct drm_i915_private *dev_priv = bus->dev_priv; in intel_gpio_post_xfer() local
319 struct drm_i915_private *dev_priv = bus->dev_priv; in intel_gpio_setup() local
599 struct drm_i915_private *dev_priv = bus->dev_priv; in do_gmbus_xfer() local
730 struct drm_i915_private *dev_priv = bus->dev_priv; in gmbus_xfer() local
755 struct drm_i915_private *dev_priv = bus->dev_priv; in intel_gmbus_output_aksv() local
809 struct drm_i915_private *dev_priv = bus->dev_priv; in gmbus_lock_bus() local
818 struct drm_i915_private *dev_priv = bus->dev_priv; in gmbus_trylock_bus() local
827 struct drm_i915_private *dev_priv = bus->dev_priv; in gmbus_unlock_bus() local
875 bus->dev_priv = dev_priv; in intel_gmbus_setup()
[all …]
A Dintel_display_power.c492 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in icl_combo_phy_aux_power_well_enable()
524 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv)); in icl_combo_phy_aux_power_well_disable()
717 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) && in hsw_power_well_enabled()
737 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), in assert_can_enable_dc9()
751 drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv), in assert_can_disable_dc9()
817 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen9_dc_mask()
1075 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) in gen9_enable_dc5()
1102 if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) in skl_enable_dc6()
1207 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in gen9_disable_dc_states()
4992 else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) in get_allowed_dc_mask()
[all …]
A Dintel_hotplug.c161 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
165 drm_dbg_kms(&dev_priv->drm, in intel_hpd_irq_storm_detect()
196 drm_info(&dev_priv->drm, in intel_hpd_irq_storm_switch_to_polling()
245 drm_dbg(&dev_priv->drm, in intel_hpd_irq_storm_reenable_work()
502 drm_dbg(&dev_priv->drm, in intel_hpd_irq_handler()
531 drm_WARN_ONCE(&dev_priv->drm, !HAS_GMCH(dev_priv), in intel_hpd_irq_handler()
575 queue_work(dev_priv->hotplug.dp_wq, &dev_priv->hotplug.dig_port_work); in intel_hpd_irq_handler()
598 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_init()
676 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_poll_enable()
711 if (!HAS_DISPLAY(dev_priv)) in intel_hpd_poll_disable()
[all …]
A Dintel_combo_phy.c96 drm_dbg(&dev_priv->drm, in check_phy_reg()
150 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phy_enabled()
205 else if (IS_ALDERLAKE_S(dev_priv)) in phy_is_master()
207 else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) in phy_is_master()
222 if (DISPLAY_VER(dev_priv) >= 12) { in icl_combo_phy_verify_state()
240 if (IS_JSL_EHL(dev_priv)) { in icl_combo_phy_verify_state()
316 drm_dbg(&dev_priv->drm, in icl_combo_phys_init()
322 if (!has_phy_misc(dev_priv, phy)) in icl_combo_phys_init()
385 if (IS_TIGERLAKE(dev_priv) || IS_DG1(dev_priv)) { in icl_combo_phys_uninit()
391 drm_dbg_kms(&dev_priv->drm, in icl_combo_phys_uninit()
[all …]
A Dintel_dpio_phy.c307 drm_err(&dev_priv->drm, in bxt_ddi_phy_set_signal_levels()
334 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
341 drm_dbg(&dev_priv->drm, in bxt_ddi_phy_is_enabled()
377 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); in _bxt_ddi_phy_init()
385 drm_dbg(&dev_priv->drm, in _bxt_ddi_phy_init()
443 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, in _bxt_ddi_phy_init()
670 vlv_dpio_get(dev_priv); in chv_set_phy_signal_level()
751 vlv_dpio_put(dev_priv); in chv_set_phy_signal_level()
821 vlv_dpio_get(dev_priv); in chv_phy_pre_pll_enable()
876 vlv_dpio_put(dev_priv); in chv_phy_pre_pll_enable()
[all …]
/linux/drivers/gpu/drm/r128/
A Dr128_cce.c212 if (GET_RING_HEAD(dev_priv) == dev_priv->ring.tail) { in r128_do_cce_idle()
238 dev_priv->cce_mode | dev_priv->ring.size_l2qw in r128_do_cce_start()
361 if (dev_priv == NULL) in r128_do_init_cce()
451 dev_priv->front_pitch_offset_c = (((dev_priv->front_pitch / 8) << 21) | in r128_do_init_cce()
453 dev_priv->back_pitch_offset_c = (((dev_priv->back_pitch / 8) << 21) | in r128_do_init_cce()
455 dev_priv->depth_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | in r128_do_init_cce()
458 dev_priv->span_pitch_offset_c = (((dev_priv->depth_pitch / 8) << 21) | in r128_do_init_cce()
545 dev_priv->ring.start = (u32 *) dev_priv->cce_ring->handle; in r128_do_init_cce()
546 dev_priv->ring.end = ((u32 *) dev_priv->cce_ring->handle in r128_do_init_cce()
551 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; in r128_do_init_cce()
[all …]
/linux/drivers/gpu/drm/mga/
A Dmga_dma.c301 dev_priv->head = dev_priv->tail = NULL; in mga_freelist_cleanup()
415 if (!dev_priv) in mga_driver_load()
595 dev_priv->warp->handle, dev_priv->primary->handle, in mga_do_agp_dma_bootstrap()
730 err = drm_legacy_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size, in mga_do_dma_bootstrap()
901 dev_priv->prim.status = (u32 *) dev_priv->status->handle; in mga_do_init_dma()
913 dev_priv->prim.start = (u8 *) dev_priv->primary->handle; in mga_do_init_dma()
914 dev_priv->prim.end = ((u8 *) dev_priv->primary->handle in mga_do_init_dma()
916 dev_priv->prim.size = dev_priv->primary->size; in mga_do_init_dma()
919 dev_priv->prim.space = dev_priv->prim.size; in mga_do_init_dma()
927 dev_priv->prim.status[0] = dev_priv->primary->offset; in mga_do_init_dma()
[all …]
/linux/drivers/gpu/drm/gma500/
A Dpsb_drv.c155 psb_spank(dev_priv); in psb_do_init()
183 if (dev_priv->mmu) { in psb_driver_unload()
189 (dev_priv->mmu), in psb_driver_unload()
245 pg = &dev_priv->gtt; in psb_driver_load()
249 dev_priv->num_pipe = dev_priv->ops->pipes; in psb_driver_load()
253 dev_priv->vdc_reg = in psb_driver_load()
283 dev_priv->aux_reg = dev_priv->vdc_reg; in psb_driver_load()
286 dev_priv->gmbus_reg = dev_priv->aux_reg; in psb_driver_load()
308 dev_priv->gmbus_reg = dev_priv->vdc_reg; in psb_driver_load()
335 if (!dev_priv->mmu) in psb_driver_load()
[all …]

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