| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| A D | rv1_clk_mgr.c | 45 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz; in rv1_determine_dppclk_threshold()
53 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
59 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
63 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
72 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
78 return new_clocks->dispclk_khz; in rv1_determine_dppclk_threshold()
185 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz; in ramp_up_dispclk_with_dpp()
227 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz in rv1_update_clocks()
275 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) in rv1_update_clocks()
276 || new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) { in rv1_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| A D | dcn201_clk_mgr.c | 91 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { in dcn201_update_clocks_vbios()
92 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn201_update_clocks_vbios()
102 dce_clk_params.target_clock_frequency = new_clocks->dispclk_khz; in dcn201_update_clocks_vbios()
141 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn201_update_clocks()
188 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn201_update_clocks()
189 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn201_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| A D | dcn20_clk_mgr.c | 133 * clk_mgr->base.dentist_vco_freq_khz / clk_mgr->base.clks.dispclk_khz; in dcn20_update_clocks_update_dentist()
232 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn2_update_clocks()
305 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn2_update_clocks()
306 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn2_update_clocks()
315 …ks->disp_dpp_voltage_level_khz = new_clocks->dispclk_khz > new_clocks->dppclk_khz ? new_clocks->di… in dcn2_update_clocks()
340 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in dcn2_update_clocks()
383 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr->clks.dispclk_khz)) { in dcn2_update_clocks_fpga()
384 clk_mgr->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn2_update_clocks_fpga()
442 clk_mgr_base->clks.dispclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn2_read_clocks_from_hw_dentist()
460 clock_cfg->current_clock_khz = clk_mgr->clks.dispclk_khz; in dcn2_get_clock()
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| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| A D | dce_clk_mgr.c | 227 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
237 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
652 pp_display_cfg->disp_clk_khz = dc->res_pool->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
676 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
692 clk_mgr->clks.dispclk_khz = patched_disp_clk; in dce_update_clocks()
703 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
719 clk_mgr->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
730 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
746 clk_mgr->clks.dispclk_khz = patched_disp_clk; in dce112_update_clocks()
758 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce120/ |
| A D | dce120_clk_mgr.c | 91 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce12_update_clocks()
97 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce12_update_clocks()
107 clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk); in dce12_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/ |
| A D | dce60_clk_mgr.c | 126 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce60_update_clocks()
140 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce60_update_clocks()
142 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce60_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| A D | dce110_clk_mgr.c | 231 pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
269 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
271 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce11_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| A D | dcn30_clk_mgr.c | 264 if (clk_mgr_base->clks.dispclk_khz == 0 || in dcn3_update_clocks()
331 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn3_update_clocks()
332 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn3_update_clocks()
333 …_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz)); in dcn3_update_clocks()
356 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in dcn3_update_clocks()
453 if (a->dispclk_khz != b->dispclk_khz) in dcn3_are_clock_states_equal()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| A D | rn_clk_mgr.c | 196 if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) { in rn_update_clocks()
198 new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz; in rn_update_clocks()
208 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in rn_update_clocks()
209 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in rn_update_clocks()
210 …_base->clks.actual_dispclk_khz = rn_vbios_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in rn_update_clocks()
251 clk_mgr_base->clks.dispclk_khz / 1000 / 7); in rn_update_clocks()
543 if (a->dispclk_khz != b->dispclk_khz) in rn_are_clock_states_equal()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| A D | dcn31_clk_mgr.c | 213 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in dcn31_update_clocks()
216 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in dcn31_update_clocks()
217 dcn31_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in dcn31_update_clocks()
243 cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz; in dcn31_update_clocks()
301 if (a->dispclk_khz != b->dispclk_khz) in dcn31_are_clock_states_equal()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/ |
| A D | dce_clk_mgr.c | 208 if (context->bw_ctx.bw.dce.dispclk_khz > in dce_get_required_clocks_state()
218 < context->bw_ctx.bw.dce.dispclk_khz) in dce_get_required_clocks_state()
401 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce_update_clocks()
415 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce_update_clocks()
417 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/ |
| A D | dce112_clk_mgr.c | 201 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce112_update_clocks()
215 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { in dce112_update_clocks()
217 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; in dce112_update_clocks()
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| /linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_trace.h | 492 __field(int, dispclk_khz)
511 __entry->dispclk_khz = clk->dispclk_khz;
535 __entry->dispclk_khz,
569 __field(int, dispclk_khz)
581 __entry->dispclk_khz = clk->dispclk_khz;
595 __entry->dispclk_khz,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| A D | vg_clk_mgr.c | 163 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { in vg_update_clocks()
164 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; in vg_update_clocks()
165 dcn301_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); in vg_update_clocks()
480 if (a->dispclk_khz != b->dispclk_khz) in vg_are_clock_states_equal()
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| /linux/drivers/gpu/drm/amd/display/dc/core/ |
| A D | dc_debug.c | 352 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
360 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
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| /linux/drivers/gpu/drm/amd/display/dc/calcs/ |
| A D | dcn_calcs.c | 1184 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(v->dispclk * 1000); in dcn_validate_bandwidth()
1186 context->bw_ctx.bw.dcn.clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000); in dcn_validate_bandwidth()
1188 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth()
1190 context->bw_ctx.bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth()
1194 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / in dcn_validate_bandwidth()
1438 dc, DM_PP_CLOCK_TYPE_DISPLAY_CLK, clocks->dispclk_khz); in dcn_find_dcfclk_suits_all()
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| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| A D | dcn10_hw_sequencer.c | 461 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_log_hw_state()
1382 if (dc->clk_mgr->clks.dispclk_khz != 0 && dc->clk_mgr->clks.dppclk_khz != 0) { in dcn10_init_hw()
1383 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz = dc->clk_mgr->clks.dispclk_khz; in dcn10_init_hw()
2649 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn10_update_dchubp_dpp()
2650 dc->clk_mgr->clks.dispclk_khz) in dcn10_update_dchubp_dpp()
2655 dc->clk_mgr->clks.dispclk_khz / 2; in dcn10_update_dchubp_dpp()
2669 dc->clk_mgr->clks.dispclk_khz / 2 : in dcn10_update_dchubp_dpp()
2670 dc->clk_mgr->clks.dispclk_khz; in dcn10_update_dchubp_dpp()
3737 current_clocks->dispclk_khz = clk_khz; in dcn10_set_clock()
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| A D | dcn10_hw_sequencer_debug.c | 477 dc->current_state->bw_ctx.bw.dcn.clk.dispclk_khz, in dcn10_get_clock_states()
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| /linux/drivers/gpu/drm/amd/display/dc/inc/ |
| A D | core_types.h | 433 int dispclk_khz; member
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| /linux/drivers/gpu/drm/amd/display/dc/dce100/ |
| A D | dce100_resource.c | 851 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce100_validate_bandwidth()
854 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce100_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_resource.c | 880 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce60_validate_bandwidth()
883 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce60_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/dce80/ |
| A D | dce80_resource.c | 885 context->bw_ctx.bw.dce.dispclk_khz = 681000; in dce80_validate_bandwidth()
888 context->bw_ctx.bw.dce.dispclk_khz = 0; in dce80_validate_bandwidth()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc.h | 394 int dispclk_khz; member
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| /linux/drivers/gpu/drm/amd/display/dmub/inc/ |
| A D | dmub_cmd.h | 914 uint32_t dispclk_khz; /**< dispclk kHz */ member
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| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| A D | dcn20_resource.c | 3116 context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000; in dcn20_calculate_dlg_params()
3135 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz) in dcn20_calculate_dlg_params()
3136 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; in dcn20_calculate_dlg_params()
3157 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dcn20_calculate_dlg_params()
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