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/linux/drivers/clk/baikal-t1/
A Dccu-div.c92 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_var_update_clkdiv()
102 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_update_clkdiv()
123 regmap_read(div->sys_regs, div->reg_ctl, &val); in ccu_div_var_enable()
146 regmap_update_bits(div->sys_regs, div->reg_ctl, in ccu_div_gate_enable()
234 regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, val); in ccu_div_var_set_rate_slow()
342 struct ccu_div *div = bit->div; in ccu_div_dbgfs_bit_set() local
364 regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, data); in ccu_div_dbgfs_var_clkdiv_set()
383 struct ccu_div *div = bit->div; in ccu_div_dbgfs_bit_get() local
445 bits[didx].div = div; in ccu_div_var_debug_init()
472 bit->div = div; in ccu_div_gate_debug_init()
[all …]
/linux/drivers/clk/berlin/
A Dberlin2-div.c71 if (div->lock) in berlin2_div_is_enabled()
77 if (div->lock) in berlin2_div_is_enabled()
89 if (div->lock) in berlin2_div_enable()
96 if (div->lock) in berlin2_div_enable()
108 if (div->lock) in berlin2_div_disable()
115 if (div->lock) in berlin2_div_disable()
125 if (div->lock) in berlin2_div_set_parent()
144 if (div->lock) in berlin2_div_set_parent()
238 div = kzalloc(sizeof(*div), GFP_KERNEL); in berlin2_div_register()
239 if (!div) in berlin2_div_register()
[all …]
/linux/drivers/clk/ti/
A Ddivider.c85 if (clkt->div == div) in _get_table_val()
111 if (!div) { in ti_clk_divider_recalc_rate()
133 if (clkt->div == div) in _is_valid_table_div()
155 if (clkt->div == div) in _div_round_up()
157 else if (clkt->div < div) in _div_round_up()
160 if ((clkt->div - div) < (up - div)) in _div_round_up()
237 int div; in ti_clk_divider_round_rate() local
533 div = kzalloc(sizeof(*div), GFP_KERNEL); in of_ti_divider_clk_setup()
534 if (!div) in of_ti_divider_clk_setup()
558 div = kzalloc(sizeof(*div), GFP_KERNEL); in of_ti_composite_divider_clk_setup()
[all …]
/linux/drivers/clk/
A Dclk-divider.c111 if (clkt->div == div) in _get_table_val()
168 if (clkt->div == div) in _is_valid_table_div()
189 if (clkt->div == div) in _round_up_table()
191 else if (clkt->div < div) in _round_up_table()
194 if ((clkt->div - div) < (up - div)) in _round_up_table()
207 if (clkt->div == div) in _round_down_table()
209 else if (clkt->div > div) in _round_down_table()
212 if ((div - clkt->div) < (div - down)) in _round_down_table()
226 div = __roundup_pow_of_two(div); in _div_round_up()
228 div = _round_up_table(table, div); in _div_round_up()
[all …]
A Dclk-fsl-flexspi.c14 { .val = 0, .div = 1, },
15 { .val = 1, .div = 2, },
16 { .val = 2, .div = 3, },
17 { .val = 3, .div = 4, },
18 { .val = 4, .div = 5, },
19 { .val = 5, .div = 6, },
20 { .val = 6, .div = 7, },
21 { .val = 7, .div = 8, },
33 { .val = 1, .div = 2, },
34 { .val = 3, .div = 4, },
[all …]
A Dclk-milbeaut.c83 u8 div; member
105 { .div = 0 },
111 { .div = 0 },
117 { .div = 0 },
123 { .div = 0 },
129 { .div = 0 },
135 { .div = 0 },
143 { .div = 0 },
149 { .div = 0 },
468 div = kzalloc(sizeof(*div), GFP_KERNEL); in m10v_clk_hw_register_divider()
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A Dclk-cdce706.c29 #define CDCE706_DIVIDER(div) (13 + (div)) argument
50 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) argument
51 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) argument
72 unsigned div; member
179 if (hwd->div) in cdce706_pll_recalc_rate()
200 hwd->div = div; in cdce706_pll_round_rate()
215 unsigned long mul = hwd->mul, div = hwd->div; in cdce706_pll_set_rate() local
285 if (hwd->div) in cdce706_divider_recalc_rate()
314 div <= CDCE706_PLL_FREQ_MAX / rate; ++div) { in cdce706_divider_round_rate()
349 hwd->div = div; in cdce706_divider_round_rate()
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/linux/drivers/clk/imx/
A Dclk-divider-gate.c32 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate_ro()
38 div->flags, div->width); in clk_divider_gate_recalc_rate_ro()
54 val = readl(div->reg) >> div->shift; in clk_divider_gate_recalc_rate()
64 div->flags, div->width); in clk_divider_gate_recalc_rate()
83 div->width, div->flags); in clk_divider_gate_set_rate()
91 val &= ~(clk_div_mask(div->width) << div->shift); in clk_divider_gate_set_rate()
117 val = readl(div->reg); in clk_divider_enable()
119 writel(val, div->reg); in clk_divider_enable()
136 val = readl(div->reg) >> div->shift; in clk_divider_disable()
139 writel(0, div->reg); in clk_divider_disable()
[all …]
/linux/drivers/clk/sunxi/
A Dclk-sunxi.c35 u8 div; in sun4i_get_pll1_factors() local
56 else if (div < 20 || (div < 32 && (div & 1))) in sun4i_get_pll1_factors()
61 else if (div < 40 || (div < 64 && (div & 2))) in sun4i_get_pll1_factors()
159 u8 div; in sun8i_a23_get_pll1_factors() local
176 if (div < 20 || (div < 32 && (div & 1))) in sun8i_a23_get_pll1_factors()
181 else if (div < 40 || (div < 64 && (div & 2))) in sun8i_a23_get_pll1_factors()
203 u8 div; in sun4i_get_pll5_factors() local
230 u8 div; in sun6i_a31_get_pll6_factors() local
251 u32 div; in sun5i_a13_get_ahb_factors() local
348 int div; in sun4i_get_apb1_factors() local
[all …]
A Dclk-sun9i-cpus.c75 u8 div, pre_div = 1; in sun9i_a80_cpus_clk_round() local
89 if (div < 32) { in sun9i_a80_cpus_clk_round()
90 pre_div = div; in sun9i_a80_cpus_clk_round()
91 div = 1; in sun9i_a80_cpus_clk_round()
92 } else if (div < 64) { in sun9i_a80_cpus_clk_round()
94 div = 2; in sun9i_a80_cpus_clk_round()
95 } else if (div < 96) { in sun9i_a80_cpus_clk_round()
97 div = 3; in sun9i_a80_cpus_clk_round()
100 div = 4; in sun9i_a80_cpus_clk_round()
106 *divp = div - 1; in sun9i_a80_cpus_clk_round()
[all …]
/linux/drivers/clk/mxs/
A Dclk-div.c40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->round_rate(&div->divider.hw, rate, prate); in clk_div_round_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
59 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
73 struct clk_div *div; in mxs_clk_div() local
77 div = kzalloc(sizeof(*div), GFP_KERNEL); in mxs_clk_div()
78 if (!div) in mxs_clk_div()
87 div->reg = reg; in mxs_clk_div()
88 div->busy = busy; in mxs_clk_div()
90 div->divider.reg = reg; in mxs_clk_div()
[all …]
/linux/drivers/clk/bcm/
A Dclk-iproc-asiu.c32 struct iproc_asiu_div div; member
99 div_h = (val >> clk->div.high_shift) & bit_mask(clk->div.high_width); in iproc_asiu_clk_recalc_rate()
101 div_l = (val >> clk->div.low_shift) & bit_mask(clk->div.low_width); in iproc_asiu_clk_recalc_rate()
114 unsigned int div; in iproc_asiu_clk_round_rate() local
123 if (div < 2) in iproc_asiu_clk_round_rate()
126 return *parent_rate / div; in iproc_asiu_clk_round_rate()
149 if (div < 2) in iproc_asiu_clk_set_rate()
152 div_h = div_l = div >> 1; in iproc_asiu_clk_set_rate()
167 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); in iproc_asiu_clk_set_rate()
170 val &= ~(bit_mask(clk->div.low_width) << clk->div.low_shift); in iproc_asiu_clk_set_rate()
[all …]
A Dclk-kona.c85 if (divider_is_fixed(div)) in scaled_div_min()
86 return (u64)div->u.fixed; in scaled_div_min()
96 if (divider_is_fixed(div)) in scaled_div_max()
578 reg_div = bitfield_extract(reg_val, div->u.s.shift, div->u.s.width); in divider_read_scaled()
609 div->u.s.width); in __div_commit()
610 div->u.s.scaled_div = scaled_div_value(div, reg_div); in __div_commit()
616 reg_div = divider(div, div->u.s.scaled_div); in __div_commit()
627 reg_val = bitfield_replace(reg_val, div->u.s.shift, div->u.s.width, in __div_commit()
650 if (!divider_exists(div) || divider_is_fixed(div)) in div_init()
1012 struct bcm_clk_div *div = &bcm_clk->u.peri->div; in kona_peri_clk_round_rate() local
[all …]
/linux/drivers/clk/meson/
A Dclk-regmap.c72 val >>= div->shift; in clk_regmap_div_recalc_rate()
73 val &= clk_div_mask(div->width); in clk_regmap_div_recalc_rate()
74 return divider_recalc_rate(hw, prate, val, div->table, div->flags, in clk_regmap_div_recalc_rate()
75 div->width); in clk_regmap_div_recalc_rate()
92 val >>= div->shift; in clk_regmap_div_determine_rate()
96 div->width, div->flags, val); in clk_regmap_div_determine_rate()
99 return divider_determine_rate(hw, req, div->table, div->width, in clk_regmap_div_determine_rate()
100 div->flags); in clk_regmap_div_determine_rate()
111 ret = divider_get_val(rate, parent_rate, div->table, div->width, in clk_regmap_div_set_rate()
112 div->flags); in clk_regmap_div_set_rate()
[all …]
/linux/drivers/clk/ingenic/
A Dcgu.c396 div = (div_reg >> clk_info->div.shift) & in ingenic_clk_recalc_rate()
400 div = clk_info->div.div_table[div]; in ingenic_clk_recalc_rate()
402 div = (div + 1) * clk_info->div.div; in ingenic_clk_recalc_rate()
421 if (clk_info->div.div_table[i] >= div && in ingenic_clk_calc_hw_div()
456 div = clamp_t(unsigned int, div, clk_info->div.div, in ingenic_clk_calc_div()
457 clk_info->div.div << clk_info->div.bits); in ingenic_clk_calc_div()
464 div = DIV_ROUND_UP(div, clk_info->div.div); in ingenic_clk_calc_div()
465 div *= clk_info->div.div; in ingenic_clk_calc_div()
467 return div; in ingenic_clk_calc_div()
481 div = clk_info->fixdiv.div; in ingenic_clk_round_rate()
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/linux/drivers/mmc/host/
A Dmeson-mx-sdhc-clkc.c19 struct clk_divider div; member
34 { .div = 6, .val = 5, },
35 { .div = 8, .val = 7, },
36 { .div = 9, .val = 8, },
37 { .div = 10, .val = 9, },
38 { .div = 12, .val = 11, },
39 { .div = 16, .val = 15, },
40 { .div = 18, .val = 17, },
41 { .div = 34, .val = 33, },
106 clkc_data->div.shift = 0; in meson_mx_sdhc_register_clkc()
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/linux/drivers/clk/tegra/
A Dclk-divider.c24 int div; in get_div() local
29 if (div < 0) in get_div()
32 return div; in get_div()
40 int div, mul; in clk_frac_div_recalc_rate() local
52 div += mul; in clk_frac_div_recalc_rate()
65 int div, mul; in clk_frac_div_round_rate() local
72 if (div < 0) in clk_frac_div_round_rate()
84 int div; in clk_frac_div_set_rate() local
89 if (div < 0) in clk_frac_div_set_rate()
90 return div; in clk_frac_div_set_rate()
[all …]
/linux/drivers/clk/spear/
A Dspear1340_clock.c244 {.div = 0x08000},
245 {.div = 0x06a38},
246 {.div = 0x06666},
247 {.div = 0x06000},
248 {.div = 0x054FD},
249 {.div = 0x05000},
250 {.div = 0x04D18},
251 {.div = 0x04CCE},
252 {.div = 0x04000},
253 {.div = 0x039D5},
[all …]
/linux/drivers/media/platform/sti/hva/
A Dhva-debugfs.c121 u64 div; in hva_dbg_perf_begin() local
132 do_div(div, 100); in hva_dbg_perf_begin()
133 period = (u32)div; in hva_dbg_perf_begin()
154 bitrate = (u32)div; in hva_dbg_perf_begin()
178 u64 div; in hva_dbg_perf_end() local
188 do_div(div, 1000); in hva_dbg_perf_end()
189 timestamp = (u32)div; in hva_dbg_perf_end()
199 bytesused, (u32)div); in hva_dbg_perf_end()
201 do_div(div, 100); in hva_dbg_perf_end()
202 duration = (u32)div; in hva_dbg_perf_end()
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/linux/drivers/clk/sprd/
A Ddiv.c13 const struct sprd_div_internal *div, in sprd_div_helper_round_rate() argument
18 NULL, div->width, 0); in sprd_div_helper_round_rate()
27 return sprd_div_helper_round_rate(&cd->common, &cd->div, in sprd_div_round_rate()
32 const struct sprd_div_internal *div, in sprd_div_helper_recalc_rate() argument
39 val = reg >> div->shift; in sprd_div_helper_recalc_rate()
40 val &= (1 << div->width) - 1; in sprd_div_helper_recalc_rate()
43 div->width); in sprd_div_helper_recalc_rate()
56 const struct sprd_div_internal *div, in sprd_div_helper_set_rate() argument
64 div->width, 0); in sprd_div_helper_set_rate()
67 reg &= ~GENMASK(div->width + div->shift - 1, div->shift); in sprd_div_helper_set_rate()
[all …]
/linux/drivers/clk/qcom/
A Dclk-regmap-mux-div.c60 u32 *div) in mux_div_get_src_div() argument
79 *div = d; in mux_div_get_src_div()
92 unsigned int i, div, max_div; in mux_div_determine_rate() local
101 for (div = 1; div < max_div; div++) { in mux_div_determine_rate()
138 for (div = 1; div < max_div; div++) { in __mux_div_set_rate_and_parent()
146 best_div = div - 1; in __mux_div_set_rate_and_parent()
156 md->div = best_div; in __mux_div_set_rate_and_parent()
167 u32 i, div, src = 0; in mux_div_get_parent() local
169 mux_div_get_src_div(md, &src, &div); in mux_div_get_parent()
206 u32 div, src; in mux_div_recalc_rate() local
[all …]
/linux/drivers/clk/at91/
A Dclk-sam9x60-pll.c50 u8 div; member
373 sam9x60_div_pll_set_div(core, div->div, 1); in sam9x60_div_pll_set()
493 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; in sam9x60_div_pll_set_rate()
507 div->div = DIV_ROUND_CLOSEST(parent_rate, rate) - 1; in sam9x60_div_pll_set_rate_chg()
516 if (cdiv == div->div) in sam9x60_div_pll_set_rate_chg()
519 sam9x60_div_pll_set_div(core, div->div, 0); in sam9x60_div_pll_set_rate_chg()
563 div->div = div->safe_div; in sam9x60_div_pll_notifier_fn()
575 sam9x60_div_pll_set_div(&core, div->div, 0); in sam9x60_div_pll_notifier_fn()
714 div = kzalloc(sizeof(*div), GFP_KERNEL); in sam9x60_clk_register_div_pll()
715 if (!div) in sam9x60_clk_register_div_pll()
[all …]
/linux/drivers/clk/x86/
A Dclk-cgu.c188 lgm_set_clk_val(div->membase, div->reg, div->shift_gate, in lgm_clk_divider_enable_disable()
228 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL); in lgm_clk_register_divider()
229 if (!div) in lgm_clk_register_divider()
240 div->reg = reg; in lgm_clk_register_divider()
249 hw = &div->hw; in lgm_clk_register_divider()
477 if (div > 1) { in lgm_clk_get_ddiv_val()
506 div = DIV_ROUND_CLOSEST_ULL((u64)div, 5); in lgm_clk_ddiv_set_rate()
507 div = div * 2; in lgm_clk_ddiv_set_rate()
544 div = div * 2; in lgm_clk_ddiv_round_rate()
545 div = DIV_ROUND_CLOSEST_ULL((u64)div, 5); in lgm_clk_ddiv_round_rate()
[all …]
/linux/drivers/clk/zynqmp/
A Ddivider.c86 u32 div, value; in zynqmp_clk_divider_recalc_rate() local
96 value = div & 0xFFFF; in zynqmp_clk_divider_recalc_rate()
98 value = div >> 16; in zynqmp_clk_divider_recalc_rate()
229 u32 value, div; in zynqmp_clk_divider_set_rate() local
237 div = 0xffff; in zynqmp_clk_divider_set_rate()
238 div |= value << 16; in zynqmp_clk_divider_set_rate()
242 div = __ffs(div); in zynqmp_clk_divider_set_rate()
337 div = kzalloc(sizeof(*div), GFP_KERNEL); in zynqmp_clk_register_divider()
338 if (!div) in zynqmp_clk_register_divider()
366 hw = &div->hw; in zynqmp_clk_register_divider()
[all …]
/linux/drivers/clk/actions/
A Dowl-factor.c21 for (clkt = table; clkt->div; clkt++) in _get_table_maxval()
32 for (clkt = table; clkt->div; clkt++) { in _get_table_div_mul()
35 *div = clkt->div; in _get_table_div_mul()
50 for (clkt = table; clkt->div; clkt++) { in _get_table_val()
52 do_div(calc_rate, clkt->div); in _get_table_val()
125 unsigned int val, mul = 0, div = 1; in owl_factor_helper_round_rate() local
130 return *parent_rate * mul / div; in owl_factor_helper_round_rate()
149 u32 reg, val, mul, div; in owl_factor_helper_recalc_rate() local
151 div = 0; in owl_factor_helper_recalc_rate()
160 if (!div) { in owl_factor_helper_recalc_rate()
[all …]

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