| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ |
| A D | fanpwm.c | 44 u32 divs, duty; in nvkm_fanpwm_get() local
48 if (ret == 0 && divs) { in nvkm_fanpwm_get()
49 divs = max(divs, duty); in nvkm_fanpwm_get()
51 duty = divs - duty; in nvkm_fanpwm_get()
52 return (duty * 100) / divs; in nvkm_fanpwm_get()
63 u32 divs, duty; in nvkm_fanpwm_set() local
66 divs = fan->base.perf.pwm_divisor; in nvkm_fanpwm_set()
68 divs = 1; in nvkm_fanpwm_set()
71 divs /= fan->base.bios.pwm_freq; in nvkm_fanpwm_set()
76 duty = divs - duty; in nvkm_fanpwm_set()
[all …]
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| A D | gf119.c | 68 gf119_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gf119_fan_pwm_get() argument
76 *divs = nvkm_rd32(device, 0x00e114 + (indx * 8)); in gf119_fan_pwm_get()
81 *divs = nvkm_rd32(device, 0x0200d8) & 0x1fff; in gf119_fan_pwm_get()
90 gf119_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gf119_fan_pwm_set() argument
97 nvkm_wr32(device, 0x00e114 + (indx * 8), divs); in gf119_fan_pwm_set()
100 nvkm_mask(device, 0x0200d8, 0x1fff, divs); /* keep the high bits */ in gf119_fan_pwm_set()
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| A D | nv40.c | 121 nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in nv40_fan_pwm_get() argument
129 *divs = (reg & 0x00007fff); in nv40_fan_pwm_get()
136 *divs = nvkm_rd32(device, 0x0015f8); in nv40_fan_pwm_get()
149 nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in nv40_fan_pwm_set() argument
154 nvkm_mask(device, 0x0010f0, 0x7fff7fff, (duty << 16) | divs); in nv40_fan_pwm_set()
157 nvkm_wr32(device, 0x0015f8, divs); in nv40_fan_pwm_set()
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| A D | gm107.c | 34 gm107_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in gm107_fan_pwm_get() argument
37 *divs = nvkm_rd32(device, 0x10eb20) & 0x1fff; in gm107_fan_pwm_get()
43 gm107_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in gm107_fan_pwm_set() argument
46 nvkm_mask(device, 0x10eb10, 0x1fff, divs); /* keep the high bits */ in gm107_fan_pwm_set()
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| A D | nv50.c | 66 nv50_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty) in nv50_fan_pwm_get() argument
74 *divs = nvkm_rd32(device, 0x00e114 + (id * 8)); in nv50_fan_pwm_get()
83 nv50_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty) in nv50_fan_pwm_set() argument
90 nvkm_wr32(device, 0x00e114 + (id * 8), divs); in nv50_fan_pwm_set()
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| /linux/drivers/cpufreq/ |
| A D | s3c2440-cpufreq.c | 124 cfg->divs.dvs = 1; in s3c2440_cpufreq_calcdivs()
127 cfg->divs.dvs = 0; in s3c2440_cpufreq_calcdivs()
133 cfg->divs.h_divisor = hdiv; in s3c2440_cpufreq_calcdivs()
134 cfg->divs.p_divisor = pdiv; in s3c2440_cpufreq_calcdivs()
157 cfg->divs.h_divisor, cfg->divs.p_divisor); in s3c2440_cpufreq_setdivs()
165 switch (cfg->divs.h_divisor) { in s3c2440_cpufreq_setdivs()
192 if (cfg->divs.p_divisor != cfg->divs.h_divisor) in s3c2440_cpufreq_setdivs()
208 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); in s3c2440_cpufreq_setdivs()
212 int *divs, in run_freq_for() argument
220 for (div = *divs; div > 0; div = *divs++) { in run_freq_for()
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| A D | s3c2412-cpufreq.c | 78 cfg->divs.arm_divisor = armdiv; in s3c2412_cpufreq_calcdivs()
88 cfg->divs.dvs = dvs = armclk < armdiv_clk; in s3c2412_cpufreq_calcdivs()
94 __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs); in s3c2412_cpufreq_calcdivs()
115 cfg->divs.h_divisor = hdiv * armdiv; in s3c2412_cpufreq_calcdivs()
116 cfg->divs.p_divisor = pdiv * armdiv; in s3c2412_cpufreq_calcdivs()
137 if (cfg->divs.arm_divisor == 2) in s3c2412_cpufreq_setdivs()
140 clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1); in s3c2412_cpufreq_setdivs()
142 if (cfg->divs.p_divisor != cfg->divs.h_divisor) in s3c2412_cpufreq_setdivs()
148 clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk); in s3c2412_cpufreq_setdivs()
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| A D | s3c2410-cpufreq.c | 34 if (cfg->divs.h_divisor == 2) in s3c2410_cpufreq_setdivs()
37 if (cfg->divs.p_divisor != cfg->divs.h_divisor) in s3c2410_cpufreq_setdivs()
76 cfg->divs.p_divisor = pdiv; in s3c2410_cpufreq_calcdivs()
77 cfg->divs.h_divisor = hdiv; in s3c2410_cpufreq_calcdivs()
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| A D | s3c24xx-cpufreq-debugfs.c | 85 cfg->divs.h_divisor, cfg->divs.p_divisor, in info_show()
86 cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off"); in info_show()
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| A D | s3c24xx-cpufreq.c | 72 cfg->divs.h_divisor = fclk / hclk; in s3c_cpufreq_getcur()
73 cfg->divs.p_divisor = fclk / pclk; in s3c_cpufreq_getcur()
81 cfg->freq.hclk = pll / cfg->divs.h_divisor; in s3c_cpufreq_calc()
82 cfg->freq.pclk = pll / cfg->divs.p_divisor; in s3c_cpufreq_calc()
101 cfg->freq.hclk, cfg->divs.h_divisor, in s3c_cpufreq_show()
102 cfg->freq.pclk, cfg->divs.p_divisor); in s3c_cpufreq_show()
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| /linux/drivers/clk/baikal-t1/ |
| A D | clk-ccu-div.c | 119 struct ccu_div **divs; member
254 div = data->divs[idx]; in ccu_div_find_desc()
325 data->divs = kcalloc(data->divs_num, sizeof(*data->divs), GFP_KERNEL); in ccu_div_create_data()
326 if (!data->divs) { in ccu_div_create_data()
341 kfree(data->divs); in ccu_div_free_data()
403 data->divs[idx] = ccu_div_hw_register(&init); in ccu_div_clk_register()
404 if (IS_ERR(data->divs[idx])) { in ccu_div_clk_register()
405 ret = PTR_ERR(data->divs[idx]); in ccu_div_clk_register()
423 ccu_div_hw_unregister(data->divs[idx]); in ccu_div_clk_register()
435 ccu_div_hw_unregister(data->divs[idx]); in ccu_div_clk_unregister()
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| /linux/drivers/clk/ |
| A D | clk-fsl-flexspi.c | 56 const struct clk_div_table *divs; in fsl_flexspi_clk_probe() local
58 divs = device_get_match_data(dev); in fsl_flexspi_clk_probe()
59 if (!divs) in fsl_flexspi_clk_probe()
81 reg, 0, 5, 0, divs, NULL); in fsl_flexspi_clk_probe()
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| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| A D | mcp77.c | 209 int divs = 0; in mcp77_clk_calc() local
213 out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs); in mcp77_clk_calc()
220 clk->cctrl = divs << 16; in mcp77_clk_calc()
244 out = calc_P((core << 1), shader, &divs); in mcp77_clk_calc()
248 (divs + P2) <= 7) { in mcp77_clk_calc()
250 clk->sctrl = (divs + P2) << 16; in mcp77_clk_calc()
259 out = calc_P(core, vdec, &divs); in mcp77_clk_calc()
263 clk->vdiv = divs << 16; in mcp77_clk_calc()
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| /linux/crypto/ |
| A D | testmgr.c | 466 if (divs[i].proportion_of_total <= 0 || in valid_sg_divisions()
469 total += divs[i].proportion_of_total; in valid_sg_divisions()
472 if (divs[i].nosimd) in valid_sg_divisions()
476 memchr_inv(&divs[i], 0, (count - i) * sizeof(divs[0])) == NULL; in valid_sg_divisions()
918 struct test_sg_division *div = divs; in generate_random_sgl_divisions()
1138 &input, divs); in build_hash_sglist()
1262 if (divs[i]->nosimd) in test_shash_vec_cfg()
1266 if (divs[i]->nosimd) in test_shash_vec_cfg()
1274 if (divs[i]->nosimd) in test_shash_vec_cfg()
1278 if (divs[i]->nosimd) in test_shash_vec_cfg()
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| /linux/drivers/gpu/drm/msm/edp/ |
| A D | edp_ctrl.c | 1344 const struct edp_pixel_clk_div *divs; in msm_edp_ctrl_pixel_clock_valid() local
1350 divs = clk_divs[0]; in msm_edp_ctrl_pixel_clock_valid()
1352 divs = clk_divs[1]; in msm_edp_ctrl_pixel_clock_valid()
1359 clk_err = abs(divs[i].rate - pixel_rate); in msm_edp_ctrl_pixel_clock_valid()
1360 if ((divs[i].rate * err / 100) >= clk_err) { in msm_edp_ctrl_pixel_clock_valid()
1362 *pm = divs[i].m; in msm_edp_ctrl_pixel_clock_valid()
1364 *pn = divs[i].n; in msm_edp_ctrl_pixel_clock_valid()
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| /linux/arch/mips/kernel/ |
| A D | mips-r2-to-r6-emul.c | 463 MIPS_R2_STATS(divs); in div_func()
485 MIPS_R2_STATS(divs); in divu_func()
574 MIPS_R2_STATS(divs); in ddiv_func()
599 MIPS_R2_STATS(divs); in ddivu_func()
2252 (unsigned long)__this_cpu_read(mipsr2emustats.divs), in mipsr2_emul_show()
2253 (unsigned long)__this_cpu_read(mipsr2bdemustats.divs)); in mipsr2_emul_show()
2314 __this_cpu_write((mipsr2emustats).divs, 0); in mipsr2_clear_show()
2315 __this_cpu_write((mipsr2bdemustats).divs, 0); in mipsr2_clear_show()
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| /linux/drivers/i2c/busses/ |
| A D | i2c-s3c2410.c | 798 unsigned int *div1, unsigned int *divs) in s3c24xx_i2c_calcdivisor() argument
816 *divs = calc_divs; in s3c24xx_i2c_calcdivisor()
831 unsigned int divs, div1; in s3c24xx_i2c_clockrate() local
845 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); in s3c24xx_i2c_clockrate()
858 iiccon |= (divs-1); in s3c24xx_i2c_clockrate()
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| /linux/drivers/clk/rockchip/ |
| A D | clk-cpu.c | 104 for (i = 0; i < ARRAY_SIZE(rate->divs); i++) { in rockchip_cpuclk_set_dividers()
105 const struct rockchip_cpuclk_clksel *clksel = &rate->divs[i]; in rockchip_cpuclk_set_dividers()
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| A D | clk-rk3188.c | 131 .divs = { \
170 .divs = { \
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| A D | clk-rk3368.c | 204 .divs = { \
214 .divs = { \
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| A D | clk-rk3036.c | 93 .divs = { \
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| /linux/arch/mips/include/asm/ |
| A D | mips-r2-to-r6-emul.h | 17 u64 divs; member
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| /linux/include/linux/soc/samsung/ |
| A D | s3c-cpufreq-core.h | 122 struct s3c_clkdivs divs; member
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| /linux/drivers/scsi/ufs/ |
| A D | ufs-exynos.c | 501 const int divs[] = {32, 16, 8, 4}; in exynos_ufs_calc_pwm_clk_div() local
506 for (i = 0; i < ARRAY_SIZE(divs); i++) { in exynos_ufs_calc_pwm_clk_div()
507 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div); in exynos_ufs_calc_pwm_clk_div()
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| /linux/arch/m68k/ifpsp060/src/ |
| A D | ilsp.S | 105 # divs.l #
195 tst.b POSNEG(%a6) # do divs, divu separately
198 # it was a divs.l, so ccode setting is a little more complicated...
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