| /linux/drivers/gpu/drm/amd/display/dc/dce110/ |
| A D | dce110_compressor.c | 122 value = dm_read_reg(cp110->base.ctx, addr); in wait_for_fbc_state_changed()
148 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
163 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
170 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_power_up_fbc()
201 value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_enable_fbc()
250 reg_data = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce110_compressor_disable_fbc()
275 value = dm_read_reg(compressor->ctx, mmFBC_STATUS); in dce110_compressor_is_fbc_enabled_in_hw()
282 value = dm_read_reg(compressor->ctx, mmFBC_MISC); in dce110_compressor_is_fbc_enabled_in_hw()
284 value = dm_read_reg(compressor->ctx, mmFBC_CNTL); in dce110_compressor_is_fbc_enabled_in_hw()
354 uint32_t value = dm_read_reg(compressor->ctx, addr); in dce110_compressor_set_fbc_invalidation_triggers()
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| A D | dce110_mem_input_v.c | 45 value = dm_read_reg( in set_flip_control()
371 value = dm_read_reg( in program_pixel_format()
424 value = dm_read_reg( in program_pixel_format()
444 value = dm_read_reg( in program_pixel_format()
667 wm_mask_cntl = dm_read_reg(ctx, wm_addr); in program_urgency_watermark()
690 wm_mask_cntl = dm_read_reg(ctx, wm_addr); in program_urgency_watermark()
750 wm_mask_cntl = dm_read_reg(ctx, wm_addr); in program_stutter_watermark()
784 wm_mask_cntl = dm_read_reg(ctx, wm_addr); in program_stutter_watermark()
830 value = dm_read_reg(ctx, wm_mask_ctrl_addr); in program_nbp_watermark()
980 value = dm_read_reg(mi->ctx, addr); in dce110_allocate_mem_input_v()
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| A D | dce110_timing_generator_v.c | 84 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
102 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
147 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_is_in_vertical_blank()
259 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
268 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
277 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
300 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
331 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
357 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
374 value = dm_read_reg(ctx, addr); in dce110_timing_generator_v_program_blanking()
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| A D | dce110_timing_generator.c | 100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
113 regval = dm_read_reg(tg->ctx, address); in dce110_timing_generator_set_early_control()
199 value = dm_read_reg(tg->ctx, addr);
261 regval = dm_read_reg(tg->ctx, in program_horz_count_by_2()
619 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
628 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
640 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
649 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
658 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
681 value = dm_read_reg(ctx, addr); in dce110_timing_generator_program_blanking()
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| A D | dce110_opp_regamma_v.c | 39 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
73 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
90 value = dm_read_reg(xfm_dce->base.ctx, in set_bypass_input_gamma()
523 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in dce110_opp_power_on_regamma_lut_v()
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| A D | dce110_opp_csc_v.c | 114 uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL); in program_color_matrix_v()
366 uint32_t value = dm_read_reg(ctx, addr); in configure_graphics_mode_v()
465 uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL); in set_Denormalization()
555 value = dm_read_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL); in program_input_csc()
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| A D | dce110_transform_v.c | 279 value = dm_read_reg(xfm_dce->base.ctx, mmSCLV_UPDATE); in set_coeff_update_complete()
303 power_ctl = dm_read_reg(ctx, mmDCFEV_MEM_PWR_CTRL); in program_multi_taps_filter()
311 dm_read_reg(ctx, mmDCFEV_MEM_PWR_STATUS), in program_multi_taps_filter()
510 value = dm_read_reg(xfm_dce->base.ctx, mmLBV_MEMORY_CTRL); in dce110_xfmv_power_up_line_buffer()
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| /linux/drivers/gpu/drm/amd/display/dc/dce112/ |
| A D | dce112_compressor.c | 302 value = dm_read_reg(cp110->base.ctx, addr); in wait_for_fbc_state_changed()
325 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
340 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
347 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_power_up_fbc()
553 dm_read_reg( in dce112_compressor_disable_lpt()
568 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_disable_lpt()
578 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_disable_lpt()
588 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_disable_lpt()
606 value = dm_read_reg(compressor->ctx, in dce112_compressor_enable_lpt()
618 value = dm_read_reg(compressor->ctx, addr); in dce112_compressor_enable_lpt()
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| /linux/drivers/gpu/drm/amd/display/dc/ |
| A D | dc_helper.c | 265 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex()
303 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get()
312 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get2()
323 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get3()
336 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get4()
351 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get5()
368 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get6()
387 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get7()
408 uint32_t reg_val = dm_read_reg(ctx, addr); in generic_reg_get8()
482 reg_val = dm_read_reg(ctx, addr); in generic_reg_wait()
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| /linux/drivers/gpu/drm/amd/display/dc/dce60/ |
| A D | dce60_timing_generator.c | 92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
130 uint32_t value = dm_read_reg(tg->ctx, addr); in dce60_timing_generator_enable_advanced_request()
133 uint32_t value2 = dm_read_reg(tg->ctx, addr2); in dce60_timing_generator_enable_advanced_request()
186 value = dm_read_reg(tg->ctx, addr); in dce60_is_tg_enabled()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/ |
| A D | irq_service.c | 98 uint32_t value = dm_read_reg(irq_service->ctx, addr); in dal_irq_service_set_generic()
135 uint32_t value = dm_read_reg(irq_service->ctx, addr); in dal_irq_service_ack_generic()
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| /linux/drivers/net/usb/ |
| A D | dm9601.c | 72 static int dm_read_reg(struct usbnet *dev, u8 reg, u8 *value) in dm_read_reg() function
124 ret = dm_read_reg(dev, DM_SHARED_CTRL, &tmp); in dm_read_shared_word()
167 ret = dm_read_reg(dev, DM_SHARED_CTRL, &tmp); in dm_write_shared_word()
403 if (dm_read_reg(dev, DM_CHIP_ID, &id) < 0) { in dm9601_bind()
413 if (dm_read_reg(dev, DM_MODE_CTRL, &mode) < 0) { in dm9601_bind()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn20/ |
| A D | irq_service_dcn20.c | 150 value = dm_read_reg(irq_service->ctx, addr); in dc_get_hpd_state_dcn20()
165 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
174 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/dce80/ |
| A D | dce80_timing_generator.c | 92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
130 uint32_t value = dm_read_reg(tg->ctx, addr); in dce80_timing_generator_enable_advanced_request()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/ |
| A D | irq_service_dcn21.c | 153 value = dm_read_reg(irq_service->ctx, addr); in dc_get_hpd_state_dcn21()
168 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
177 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce80/ |
| A D | irq_service_dce80.c | 47 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
56 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce120/ |
| A D | irq_service_dce120.c | 47 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
56 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn303/ |
| A D | irq_service_dcn303.c | 60 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
65 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce60/ |
| A D | irq_service_dce60.c | 54 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
63 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/ |
| A D | irq_service_dcn201.c | 91 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
100 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dce110/ |
| A D | irq_service_dce110.c | 48 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
55 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| A D | irq_service_dcn10.c | 140 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
149 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/ |
| A D | irq_service_dcn30.c | 149 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
158 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/ |
| A D | irq_service_dcn302.c | 132 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
137 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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| /linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/ |
| A D | irq_service_dcn31.c | 137 uint32_t value = dm_read_reg(irq_service->ctx, addr); in hpd_ack()
146 value = dm_read_reg(irq_service->ctx, info->enable_reg); in hpd_ack()
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