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Searched refs:dml (Results 1 – 19 of 19) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dml/
A DMakefile57 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
60 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
61 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/dcn20_fpu.o := $(dml_ccflags)
73 CFLAGS_$(AMDDALPATH)/dc/dml/dcn301/dcn301_fpu.o := $(dml_ccflags)
74 CFLAGS_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_ccflags)
75 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
76 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_rcflags)
77 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dcn2x/dcn2x.o := $(dml_rcflags)
89 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_rcflags)
93 CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn301/
A Ddcn301_fpu.c220 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel() argument
226 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
229 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz; in calculate_wm_set_for_vlevel()
230 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz; in calculate_wm_set_for_vlevel()
232 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us; in calculate_wm_set_for_vlevel()
233 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us; in calculate_wm_set_for_vlevel()
236 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000; in calculate_wm_set_for_vlevel()
353 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg()
358 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg()
363 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn301_calculate_wm_and_dlg()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn31/
A Ddcn31_resource.c1830 context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE; in dcn31_populate_dml_pipes_from_context()
1837 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192; in dcn31_populate_dml_pipes_from_context()
1861 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb]; in dcn31_calculate_wm_and_dlg_fp()
1863 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn31_calculate_wm_and_dlg_fp()
1864 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn31_calculate_wm_and_dlg_fp()
1877 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
1886 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz; in dcn31_calculate_wm_and_dlg_fp()
2039 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn31_validate_bandwidth()
2119 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn31_update_bw_bounding_box()
2122 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31); in dcn31_update_bw_bounding_box()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_resource.c1515 if (dc->dml.ip.writeback_max_hscl_taps > 1) { in dcn30_populate_dml_writeback_from_context()
1599 struct display_mode_lib *dml = &context->bw_ctx.dml; in dcn30_set_mcif_arb_params() local
1874 struct vba_vars_st *vba = &context->bw_ctx.dml.vba; in dcn30_internal_validate_bw()
1901 if (vlevel < context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
1917 if (vlevel < context->bw_ctx.dml.soc.num_states) { in dcn30_internal_validate_bw()
1924 dml_log_mode_support_params(&context->bw_ctx.dml); in dcn30_internal_validate_bw()
1926 if (vlevel == context->bw_ctx.dml.soc.num_states) in dcn30_internal_validate_bw()
2136 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk) in dcn30_calculate_wm_and_dlg_fp()
2137 dcfclk = context->bw_ctx.dml.soc.min_dcfclk; in dcn30_calculate_wm_and_dlg_fp()
2198 …if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == … in dcn30_calculate_wm_and_dlg_fp()
[all …]
A Ddcn30_hwseq.c292 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; in dcn30_mmhubbub_warmup()
308 warmup_params.address_increment = dc->dml.soc.vmm_page_size_bytes; in dcn30_mmhubbub_warmup()
/linux/net/packet/
A Ddiag.c49 struct packet_diag_mclist *dml; in pdiag_put_mclist() local
51 dml = nla_reserve_nohdr(nlskb, sizeof(*dml)); in pdiag_put_mclist()
52 if (!dml) { in pdiag_put_mclist()
58 dml->pdmc_index = ml->ifindex; in pdiag_put_mclist()
59 dml->pdmc_type = ml->type; in pdiag_put_mclist()
60 dml->pdmc_alen = ml->alen; in pdiag_put_mclist()
61 dml->pdmc_count = ml->count; in pdiag_put_mclist()
62 BUILD_BUG_ON(sizeof(dml->pdmc_addr) != sizeof(ml->addr)); in pdiag_put_mclist()
63 memcpy(dml->pdmc_addr, ml->addr, sizeof(ml->addr)); in pdiag_put_mclist()
/linux/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_resource.c1038 struct display_mode_lib *dml, in calculate_wm_set_for_vlevel() argument
1044 ASSERT(vlevel < dml->soc.num_states); in calculate_wm_set_for_vlevel()
1122 … context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn21_calculate_wm()
1131 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_… in dcn21_calculate_wm()
1162 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_calculate_wm()
1167 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_calculate_wm()
1172 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_calculate_wm()
1178 &context->bw_ctx.dml, pipes, pipe_cnt); in dcn21_calculate_wm()
1291 … context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; in dcn21_fast_validate_bw()
1316 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn21_fast_validate_bw()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/calcs/
A Ddcn_calcs.c458 struct display_mode_lib *dml = (struct display_mode_lib *)(&dc->dml); in dcn_bw_calc_rq_dlg_ttu() local
509 dml1_extract_rq_regs(dml, rq_regs, rq_param); in dcn_bw_calc_rq_dlg_ttu()
511 dml, in dcn_bw_calc_rq_dlg_ttu()
1313 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = in dcn_validate_bandwidth()
1758 dc->dml.soc.ideal_dram_bw_after_urgent_percent = in dcn_bw_sync_calcs_and_dml()
1762 dc->dml.soc.round_trip_ping_latency_dcfclk_cycles = in dcn_bw_sync_calcs_and_dml()
1786 dc->dml.ip.max_num_dpp = dc->dcn_ip->max_num_dpp; in dcn_bw_sync_calcs_and_dml()
1787 dc->dml.ip.max_num_wb = dc->dcn_ip->max_num_writeback; in dcn_bw_sync_calcs_and_dml()
1794 dc->dml.ip.max_hscl_taps = dc->dcn_ip->max_hscl_taps; in dcn_bw_sync_calcs_and_dml()
1795 dc->dml.ip.max_vscl_taps = dc->dcn_ip->max_vscl_taps; in dcn_bw_sync_calcs_and_dml()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_resource.c2904 … context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2; in dcn20_fast_validate_bw()
2929 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = in dcn20_fast_validate_bw()
2961 …s[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx… in dcn20_calculate_wm()
2965 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx]; in dcn20_calculate_wm()
2974 …context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from… in dcn20_calculate_wm()
3127 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] in dcn20_calculate_dlg_params()
3165 …bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] … in dcn20_calculate_dlg_params()
3173 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml, in dcn20_calculate_dlg_params()
3183 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml, in dcn20_calculate_dlg_params()
3229 …dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_st… in dcn20_validate_bandwidth_internal()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
A Ddcn30_clk_mgr.c110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us; in dcn3_build_wm_range_table()
111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us; in dcn3_build_wm_range_table()
112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us; in dcn3_build_wm_range_table()
139 …able.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_la… in dcn3_build_wm_range_table()
/linux/drivers/gpu/drm/amd/display/dc/
A DMakefile31 DC_LIBS += dcn10 dml
A Ddc.h724 struct display_mode_lib dml; member
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_resource.c1351 struct display_mode_lib *dml = &dc->dml; in dcn10_resource_construct_fp() local
1353 dml->ip.max_num_dpp = 3; in dcn10_resource_construct_fp()
1533 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1); in dcn10_resource_construct()
1644 dc->dml.ip.max_num_dpp = pool->base.pipe_count; in dcn10_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc.c1958 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); in init_state()
3275 struct display_mode_lib *dml; in dc_set_power_state() local
3304 dml = kzalloc(sizeof(struct display_mode_lib), in dc_set_power_state()
3307 ASSERT(dml); in dc_set_power_state()
3308 if (!dml) in dc_set_power_state()
3314 memcpy(dml, &dc->current_state->bw_ctx.dml, sizeof(struct display_mode_lib)); in dc_set_power_state()
3321 dc->current_state->bw_ctx.dml = *dml; in dc_set_power_state()
3323 kfree(dml); in dc_set_power_state()
/linux/drivers/gpu/drm/amd/display/dc/dcn302/
A Ddcn302_resource.c1304 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn302_update_bw_bounding_box()
1420 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_update_bw_bounding_box()
1422 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_update_bw_bounding_box()
1623 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30); in dcn302_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/dcn303/
A Ddcn303_resource.c1234 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0; in dcn303_update_bw_bounding_box()
1362 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_update_bw_bounding_box()
1364 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_update_bw_bounding_box()
1554 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30); in dcn303_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/inc/
A Dcore_types.h455 struct display_mode_lib dml; member
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_resource.c1188 dml_init_instance(&dc->dml, &dcn201_soc, &dcn201_ip, DML_PROJECT_DCN201); in dcn201_resource_construct()
/linux/drivers/gpu/drm/amd/display/dc/dcn301/
A Ddcn301_resource.c1560 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30); in dcn301_resource_construct()

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