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Searched refs:dpcd (Results 1 – 25 of 41) sorted by relevance

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/linux/drivers/gpu/drm/
A Ddrm_dp_helper.c512 dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_downstream_is_type()
720 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) in drm_dp_read_downstream_info()
757 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_dotclock()
787 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_tmds_clock()
852 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_min_tmds_clock()
895 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_max_bpc()
950 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_420_passthrough()
981 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_444_to_420_conversion()
1013 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_rgb_to_ycbcr_conversion()
1049 if (!drm_dp_is_branch(dpcd)) in drm_dp_downstream_mode()
[all …]
/linux/drivers/gpu/drm/nouveau/
A Dnouveau_dp.c43 return drm_dp_read_sink_count_cap(connector, outp->dp.dpcd, &outp->dp.desc); in nouveau_dp_has_sink_count()
55 u8 *dpcd = outp->dp.dpcd; in nouveau_dp_probe_dpcd() local
57 ret = drm_dp_read_dpcd_caps(aux, dpcd); in nouveau_dp_probe_dpcd()
61 ret = drm_dp_read_desc(aux, &outp->dp.desc, drm_dp_is_branch(dpcd)); in nouveau_dp_probe_dpcd()
68 mstm->can_mst = drm_dp_read_mst_cap(aux, dpcd); in nouveau_dp_probe_dpcd()
86 ret = drm_dp_read_downstream_info(aux, dpcd, in nouveau_dp_probe_dpcd()
109 u8 *dpcd = nv_encoder->dp.dpcd; in nouveau_dp_detect() local
116 dpcd[DP_DPCD_REV] != 0) in nouveau_dp_detect()
146 nv_encoder->dp.link_bw = 27000 * dpcd[DP_MAX_LINK_RATE]; in nouveau_dp_detect()
148 dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK; in nouveau_dp_detect()
[all …]
A Dnouveau_encoder.h80 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
/linux/include/drm/
A Ddrm_dp_helper.h1534 const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
1751 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_enhanced_frame_cap()
1758 return dpcd[DP_DPCD_REV] >= 0x11 && in drm_dp_fast_training_cap()
1765 return dpcd[DP_DPCD_REV] >= 0x12 && in drm_dp_tps3_supported()
1772 return dpcd[DP_DPCD_REV] >= 0x14 && in drm_dp_tps4_supported()
1836 return dpcd[DP_EDP_CONFIGURATION_CAP] & in drm_dp_alternate_scrambler_reset_cap()
1844 return dpcd[DP_DOWN_STREAM_PORT_COUNT] & in drm_dp_sink_can_do_video_without_timing_msa()
2060 u8 dpcd[DP_RECEIVER_CAP_SIZE]);
2073 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2109 const u8 *dpcd,
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
A Datombios_dp.c252 const u8 dpcd[DP_DPCD_SIZE], in amdgpu_atombios_dp_get_dp_link_config()
259 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in amdgpu_atombios_dp_get_dp_link_config()
338 if (dig_connector->dpcd[DP_DPCD_REV] > 0x10) { in amdgpu_atombios_dp_ds_ports()
358 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in amdgpu_atombios_dp_get_dpcd()
361 dig_connector->dpcd); in amdgpu_atombios_dp_get_dpcd()
368 dig_connector->dpcd[0] = 0; in amdgpu_atombios_dp_get_dpcd()
480 if (dig_connector->dpcd[0] >= 0x11) { in amdgpu_atombios_dp_set_rx_power_state()
494 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
548 if (dp_info->dpcd[3] & 0x1) in amdgpu_atombios_dp_link_train_init()
560 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in amdgpu_atombios_dp_link_train_init()
[all …]
/linux/drivers/gpu/drm/bridge/analogix/
A Danalogix-anx6345.c64 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
100 u8 dp_bw, dpcd[2]; in anx6345_dp_link_training() local
151 if (anx6345->dpcd[DP_DPCD_REV] >= 0x11) { in anx6345_dp_link_training()
159 dpcd[0] &= ~DP_SET_POWER_MASK; in anx6345_dp_link_training()
160 dpcd[0] |= DP_SET_POWER_D0; in anx6345_dp_link_training()
213 dpcd[0] = dp_bw; in anx6345_dp_link_training()
215 SP_DP_MAIN_LINK_BW_SET_REG, dpcd[0]); in anx6345_dp_link_training()
219 dpcd[1] = drm_dp_max_lane_count(anx6345->dpcd); in anx6345_dp_link_training()
222 SP_DP_LANE_COUNT_SET_REG, dpcd[1]); in anx6345_dp_link_training()
227 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; in anx6345_dp_link_training()
[all …]
A Danalogix-anx78xx.c83 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
606 u8 dp_bw, dpcd[2]; in anx78xx_dp_link_training() local
663 if (anx78xx->dpcd[DP_DPCD_REV] >= 0x11) { in anx78xx_dp_link_training()
671 dpcd[0] &= ~DP_SET_POWER_MASK; in anx78xx_dp_link_training()
672 dpcd[0] |= DP_SET_POWER_D0; in anx78xx_dp_link_training()
714 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
727 anx78xx->dpcd[DP_MAX_LINK_RATE]); in anx78xx_dp_link_training()
731 dpcd[1] = drm_dp_max_lane_count(anx78xx->dpcd); in anx78xx_dp_link_training()
733 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd)) in anx78xx_dp_link_training()
734 dpcd[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; in anx78xx_dp_link_training()
[all …]
/linux/drivers/gpu/drm/msm/dp/
A Ddp_panel.c29 u8 *dpcd, major = 0, minor = 0, temp; in dp_panel_read_dpcd() local
32 dpcd = dp_panel->dpcd; in dp_panel_read_dpcd()
38 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
49 temp = dpcd[DP_TRAINING_AUX_RD_INTERVAL]; in dp_panel_read_dpcd()
58 dpcd, (DP_RECEIVER_CAP_SIZE + 1)); in dp_panel_read_dpcd()
69 link_info->revision = dpcd[DP_DPCD_REV]; in dp_panel_read_dpcd()
73 link_info->rate = drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]); in dp_panel_read_dpcd()
87 if (drm_dp_enhanced_frame_cap(dpcd)) in dp_panel_read_dpcd()
90 dp_panel->dfp_present = dpcd[DP_DOWNSTREAMPORT_PRESENT]; in dp_panel_read_dpcd()
93 if (dp_panel->dfp_present && (dpcd[DP_DPCD_REV] > 0x10)) { in dp_panel_read_dpcd()
[all …]
A Ddp_ctrl.c122 u8 *dpcd = ctrl->panel->dpcd; in dp_ctrl_config_ctrl() local
128 if (dpcd[DP_EDP_CONFIGURATION_CAP] & DP_ALTERNATE_SCRAMBLER_RESET_CAP) in dp_ctrl_config_ctrl()
145 if (drm_dp_enhanced_frame_cap(dpcd)) in dp_ctrl_config_ctrl()
1099 drm_dp_link_train_clock_recovery_delay(ctrl->aux, ctrl->panel->dpcd); in dp_ctrl_link_train_1()
1177 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); in dp_ctrl_clear_training_pattern()
1192 if (drm_dp_tps3_supported(ctrl->panel->dpcd)) in dp_ctrl_link_train_2()
1204 drm_dp_link_train_channel_eq_delay(ctrl->aux, ctrl->panel->dpcd); in dp_ctrl_link_train_2()
1409 u8 *dpcd = ctrl->panel->dpcd; in dp_ctrl_use_fixed_nvid() local
1415 if (drm_dp_is_branch(dpcd)) in dp_ctrl_use_fixed_nvid()
A Ddp_panel.h39 u8 dpcd[DP_RECEIVER_CAP_SIZE + 1]; member
/linux/drivers/gpu/drm/radeon/
A Datombios_dp.c307 const u8 dpcd[DP_DPCD_SIZE], in radeon_dp_get_dp_link_config()
313 unsigned max_link_rate = drm_dp_max_link_rate(dpcd); in radeon_dp_get_dp_link_config()
314 unsigned max_lane_num = drm_dp_max_lane_count(dpcd); in radeon_dp_get_dp_link_config()
396 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE); in radeon_dp_getdpcd()
399 dig_connector->dpcd); in radeon_dp_getdpcd()
406 dig_connector->dpcd[0] = 0; in radeon_dp_getdpcd()
529 if (dig_connector->dpcd[0] >= 0x11) { in radeon_dp_set_rx_power_state()
545 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
610 if (dp_info->dpcd[3] & 0x1) in radeon_dp_link_train_init()
622 if (drm_dp_enhanced_frame_cap(dp_info->dpcd)) in radeon_dp_link_train_init()
[all …]
/linux/drivers/gpu/drm/tegra/
A Ddp.c172 u8 dpcd[DP_RECEIVER_CAP_SIZE], value; in drm_dp_link_probe() local
178 err = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, sizeof(dpcd)); in drm_dp_link_probe()
182 link->revision = dpcd[DP_DPCD_REV]; in drm_dp_link_probe()
183 link->max_rate = drm_dp_max_link_rate(dpcd); in drm_dp_link_probe()
184 link->max_lanes = drm_dp_max_lane_count(dpcd); in drm_dp_link_probe()
186 link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd); in drm_dp_link_probe()
187 link->caps.tps3_supported = drm_dp_tps3_supported(dpcd); in drm_dp_link_probe()
188 link->caps.fast_training = drm_dp_fast_training_cap(dpcd); in drm_dp_link_probe()
189 link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd); in drm_dp_link_probe()
191 if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { in drm_dp_link_probe()
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/engine/disp/
A Ddp.c57 if (dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL]) in nvkm_dp_train_sense()
58 mdelay(dp->dpcd[DPCD_RC0E_AUX_RD_INTERVAL] * 4); in nvkm_dp_train_sense()
166 if (lt->dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED) in nvkm_dp_train_eq()
244 dp->dpcd[DPCD_RC02] &= ~DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
245 lt.pc2 = dp->dpcd[DPCD_RC02] & DPCD_RC02_TPS3_SUPPORTED; in nvkm_dp_train_links()
324 if (dp->dpcd[DPCD_RC03] & DPCD_RC03_MAX_DOWNSPREAD) { in nvkm_dp_train_init()
369 const u8 sink_nr = dp->dpcd[DPCD_RC02] & DPCD_RC02_MAX_LANE_COUNT; in nvkm_dp_train()
370 const u8 sink_bw = dp->dpcd[DPCD_RC01_MAX_LINK_RATE]; in nvkm_dp_train()
427 ior->dp.ef = dp->dpcd[DPCD_RC02] & DPCD_RC02_ENHANCED_FRAME_CAP; in nvkm_dp_train()
541 if (!nvkm_rdaux(aux, DPCD_RC00_DPCD_REV, dp->dpcd, in nvkm_dp_enable()
[all …]
A Ddp.h24 u8 dpcd[16]; member
/linux/drivers/gpu/drm/gma500/
A Dcdv_intel_dp.c267 uint8_t dpcd[4]; member
330 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { in cdv_intel_dp_max_lane_count()
1116 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in cdv_intel_dp_sink_dpms()
1676 sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd)) in cdv_dp_detect()
1678 if (intel_dp->dpcd[DP_DPCD_REV] != 0) in cdv_dp_detect()
1683 intel_dp->dpcd[0], intel_dp->dpcd[1], in cdv_dp_detect()
1684 intel_dp->dpcd[2], intel_dp->dpcd[3]); in cdv_dp_detect()
2075 intel_dp->dpcd, in cdv_intel_dp_init()
2076 sizeof(intel_dp->dpcd)); in cdv_intel_dp_init()
2086 intel_dp->dpcd[0], intel_dp->dpcd[1], in cdv_intel_dp_init()
[all …]
/linux/drivers/gpu/drm/msm/edp/
A Dedp_ctrl.c95 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
405 u8 max_lane = drm_dp_max_lane_count(ctrl->dpcd); in edp_fill_link_cfg()
415 ctrl->link_rate = ctrl->dpcd[DP_MAX_LINK_RATE]; in edp_fill_link_cfg()
441 if (drm_dp_enhanced_frame_cap(ctrl->dpcd)) in edp_config_ctrl()
703 max_lane = drm_dp_max_lane_count(ctrl->dpcd); in edp_link_rate_down_shift()
764 if (drm_dp_enhanced_frame_cap(ctrl->dpcd)) in edp_do_link_train()
974 if (ctrl->dpcd[DP_DPCD_REV] >= 0x11) { in edp_ctrl_on_worker()
1037 if (ctrl->dpcd[DP_DPCD_REV] >= 0x11) { in edp_ctrl_off_worker()
1222 if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd, in msm_edp_ctrl_panel_connected()
1225 memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); in msm_edp_ctrl_panel_connected()
[all …]
/linux/drivers/gpu/drm/i915/display/
A Dintel_dp.c1916 drm_dp_is_branch(intel_dp->dpcd) && in downstream_hpd_needs_d0()
1979 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) in intel_dp_set_power()
2040 if (intel_dp->dpcd[DP_DPCD_REV] == 0) in intel_dp_sync_state()
2371 if (!drm_dp_is_branch(intel_dp->dpcd)) in intel_dp_configure_protocol_converter()
2554 drm_dp_is_branch(intel_dp->dpcd)); in intel_edp_init_dpcd()
2641 intel_dp->dpcd, in intel_dp_has_sink_count()
2659 drm_dp_is_branch(intel_dp->dpcd)); in intel_dp_get_dpcd()
4065 u8 *dpcd = intel_dp->dpcd; in intel_dp_detect_dpcd() local
4077 if (!drm_dp_is_branch(dpcd)) in intel_dp_detect_dpcd()
4417 intel_dp->dpcd, in intel_dp_detect()
[all …]
A Dintel_dp_link_training.c199 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { in intel_dp_init_lttpr_and_dprx_caps()
669 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) in intel_dp_prepare_link_train()
690 drm_dp_link_train_clock_recovery_delay(&intel_dp->aux, intel_dp->dpcd); in intel_dp_link_training_clock_recovery_delay()
773 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) in intel_dp_link_training_clock_recovery()
865 drm_dp_tps4_supported(intel_dp->dpcd); in intel_dp_training_pattern()
883 drm_dp_tps3_supported(intel_dp->dpcd); in intel_dp_training_pattern()
903 drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd); in intel_dp_link_training_channel_equalization_delay()
/linux/drivers/gpu/drm/i915/gvt/
A Ddisplay.c515 kfree(port->dpcd); in clean_virtual_dp_monitor()
516 port->dpcd = NULL; in clean_virtual_dp_monitor()
548 port->dpcd = kzalloc(sizeof(*(port->dpcd)), GFP_KERNEL); in setup_virtual_dp_monitor()
549 if (!port->dpcd) { in setup_virtual_dp_monitor()
558 memcpy(port->dpcd->data, dpcd_fix_data, DPCD_HEADER_SIZE); in setup_virtual_dp_monitor()
559 port->dpcd->data_valid = true; in setup_virtual_dp_monitor()
560 port->dpcd->data[DPCD_SINK_COUNT] = 0x1; in setup_virtual_dp_monitor()
A Dhandlers.c1139 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |= in dp_aux_ch_ctl_link_training()
1145 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC; in dp_aux_ch_ctl_link_training()
1165 struct intel_vgpu_dpcd_data *dpcd = NULL; in dp_aux_ch_ctl_mmio_write() local
1194 dpcd = port->dpcd; in dp_aux_ch_ctl_mmio_write()
1243 if (dpcd && dpcd->data_valid) { in dp_aux_ch_ctl_mmio_write()
1247 dpcd->data[p] = buf[t]; in dp_aux_ch_ctl_mmio_write()
1250 dp_aux_ch_ctl_link_training(dpcd, in dp_aux_ch_ctl_mmio_write()
1258 dpcd && dpcd->data_valid); in dp_aux_ch_ctl_mmio_write()
1301 if (dpcd && dpcd->data_valid) { in dp_aux_ch_ctl_mmio_write()
1305 t = dpcd->data[addr + i - 1]; in dp_aux_ch_ctl_mmio_write()
[all …]
/linux/drivers/gpu/drm/xlnx/
A Dzynqmp_dp.c317 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
710 drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_cr()
758 if (dp->dpcd[DP_DPCD_REV] >= DP_V1_2 && in zynqmp_dp_link_train_ce()
759 dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) in zynqmp_dp_link_train_ce()
775 drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); in zynqmp_dp_link_train_ce()
809 enhanced = drm_dp_enhanced_frame_cap(dp->dpcd); in zynqmp_dp_train()
815 if (dp->dpcd[3] & 0x1) { in zynqmp_dp_train()
1306 ret = drm_dp_dpcd_read(&dp->aux, 0x0, dp->dpcd, in zynqmp_dp_connector_detect()
1307 sizeof(dp->dpcd)); in zynqmp_dp_connector_detect()
1314 drm_dp_max_link_rate(dp->dpcd), in zynqmp_dp_connector_detect()
[all …]
/linux/drivers/gpu/drm/bridge/
A Dtc358767.c233 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member
673 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, in tc_get_display_props()
678 revision = tc->link.dpcd[DP_DPCD_REV]; in tc_get_display_props()
679 rate = drm_dp_max_link_rate(tc->link.dpcd); in tc_get_display_props()
680 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); in tc_get_display_props()
716 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_get_display_props()
994 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_main_link_enable()
1041 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? in tc_main_link_enable()
1192 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) in tc_stream_enable()
/linux/drivers/gpu/drm/bridge/cadence/
A Dcdns-mhdp8546-core.c1383 u8 dpcd[DP_RECEIVER_CAP_SIZE]) in cdns_mhdp_fill_sink_caps()
1391 mhdp->sink.ssc = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1396 if (drm_dp_tps3_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1398 if (drm_dp_tps4_supported(dpcd)) in cdns_mhdp_fill_sink_caps()
1402 mhdp->sink.fast_link = !!(dpcd[DP_MAX_DOWNSPREAD] & in cdns_mhdp_fill_sink_caps()
1408 u8 dpcd[DP_RECEIVER_CAP_SIZE], amp[2]; in cdns_mhdp_link_up() local
1430 mhdp->link.revision = dpcd[0]; in cdns_mhdp_link_up()
1431 mhdp->link.rate = drm_dp_bw_code_to_link_rate(dpcd[1]); in cdns_mhdp_link_up()
1432 mhdp->link.num_lanes = dpcd[2] & DP_MAX_LANE_COUNT_MASK; in cdns_mhdp_link_up()
1434 if (dpcd[2] & DP_ENHANCED_FRAME_CAP) in cdns_mhdp_link_up()
[all …]
/linux/Documentation/devicetree/bindings/display/exynos/
A Dexynos_dp.txt67 -samsung,link-rate: deprecated prop that can reading from monitor by dpcd method.
68 -samsung,lane-count: deprecated prop that can reading from monitor by dpcd method.
/linux/drivers/gpu/drm/rockchip/
A Dcdn-dp-core.h102 u8 dpcd[DP_RECEIVER_CAP_SIZE]; member

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