/linux/drivers/gpu/drm/i915/display/ |
A D | intel_dpll.c | 317 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m() 774 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) in i9xx_dpll_compute_fp() argument 776 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; in i9xx_dpll_compute_fp() 781 return (1 << dpll->n) << 16 | dpll->m2; in pnv_dpll_compute_fp() 874 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll() 931 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll() 962 return dpll->m < factor * dpll->n; in ilk_needs_fb_cb_tune() 1072 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll() 1436 u32 dpll = crtc_state->dpll_hw_state.dpll; in i9xx_enable_pll() local 1824 const struct dpll *dpll) in vlv_force_pll_on() argument [all …]
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A D | intel_dpll.h | 11 struct dpll; 18 int vlv_calc_dpll_params(int refclk, struct dpll *clock); 19 int pnv_calc_dpll_params(int refclk, struct dpll *clock); 20 int i9xx_calc_dpll_params(int refclk, struct dpll *clock); 21 u32 i9xx_dpll_compute_fp(const struct dpll *dpll); 26 const struct dpll *dpll); 36 struct dpll *best_clock); 37 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
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A D | intel_dpll_mgr.c | 205 mutex_lock(&dev_priv->dpll.lock); in intel_enable_shared_dpll() 254 mutex_lock(&dev_priv->dpll.lock); in intel_disable_shared_dpll() 398 &dev_priv->dpll.shared_dplls[i]; in intel_shared_dpll_swap_state() 418 hw_state->dpll = val; in ibx_pch_dpll_get_hw_state() 521 hw_state->dpll, in ibx_dump_hw_state() 2083 struct dpll best_clock; in bxt_ddi_hdmi_pll_dividers() 2221 struct dpll clock; in bxt_ddi_pll_get_freq() 4100 dev_priv->dpll.mgr = dpll_mgr; in intel_shared_dpll_init() 4254 if (i915->dpll.mgr && i915->dpll.mgr->update_ref_clks) in intel_dpll_update_ref_clks() 4303 if (dev_priv->dpll.mgr) { in intel_dpll_dump_hw_state() [all …]
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A D | intel_dvo.c | 462 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init() local 499 dpll[pipe] = intel_de_read(dev_priv, DPLL(pipe)); in intel_dvo_init() 501 dpll[pipe] | DPLL_DVO_2X_MODE); in intel_dvo_init() 508 intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); in intel_dvo_init()
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A D | g4x_dp.h | 20 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915);
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A D | g4x_dp.c | 25 struct dpll dpll; member 65 const struct dpll *vlv_get_dpll(struct drm_i915_private *i915) in vlv_get_dpll() 67 return IS_CHERRYVIEW(i915) ? &chv_dpll[0].dpll : &vlv_dpll[0].dpll; in vlv_get_dpll() 94 pipe_config->dpll = divisor[i].dpll; in g4x_dp_set_clock()
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/linux/drivers/gpu/drm/gma500/ |
A D | psb_intel_display.c | 162 dpll |= in psb_intel_crtc_mode_set() 186 dpll |= 3; in psb_intel_crtc_mode_set() 214 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set() 249 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set() 250 REG_READ(map->dpll); in psb_intel_crtc_mode_set() 255 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set() 304 u32 dpll; in psb_intel_crtc_clock_get() local 311 dpll = REG_READ(map->dpll); in psb_intel_crtc_clock_get() 319 dpll = p->dpll; in psb_intel_crtc_clock_get() 336 ffs((dpll & in psb_intel_crtc_clock_get() [all …]
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A D | oaktrail_crtc.c | 248 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms() 523 dpll |= DPLL_VGA_MODE_DIS; in oaktrail_crtc_mode_set() 526 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set() 529 dpll |= DPLLA_MODE_LVDS; in oaktrail_crtc_mode_set() 537 dpll |= DPLL_DVO_HIGH_SPEED; in oaktrail_crtc_mode_set() 538 dpll |= in oaktrail_crtc_mode_set() 550 dpll |= DPLL_VCO_ENABLE; in oaktrail_crtc_mode_set() 552 if (dpll & DPLL_VCO_ENABLE) { in oaktrail_crtc_mode_set() 555 REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i); in oaktrail_crtc_mode_set() 564 REG_WRITE_WITH_AUX(map->dpll, dpll, i); in oaktrail_crtc_mode_set() [all …]
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A D | cdv_intel_display.c | 659 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set() 716 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set() 717 REG_READ(map->dpll); in cdv_intel_crtc_mode_set() 752 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set() 761 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set() 763 REG_READ(map->dpll); in cdv_intel_crtc_mode_set() 836 u32 dpll; in cdv_intel_crtc_clock_get() local 843 dpll = REG_READ(map->dpll); in cdv_intel_crtc_clock_get() 851 dpll = p->dpll; in cdv_intel_crtc_clock_get() 867 ffs((dpll & in cdv_intel_crtc_clock_get() [all …]
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A D | gma_display.c | 215 temp = REG_READ(map->dpll); in gma_crtc_dpms() 217 REG_WRITE(map->dpll, temp); in gma_crtc_dpms() 218 REG_READ(map->dpll); in gma_crtc_dpms() 222 REG_READ(map->dpll); in gma_crtc_dpms() 226 REG_READ(map->dpll); in gma_crtc_dpms() 303 temp = REG_READ(map->dpll); in gma_crtc_dpms() 306 REG_READ(map->dpll); in gma_crtc_dpms() 592 crtc_state->saveDPLL = REG_READ(map->dpll); in gma_crtc_save() 631 REG_WRITE(map->dpll, in gma_crtc_restore() 633 REG_READ(map->dpll); in gma_crtc_restore() [all …]
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A D | oaktrail_hdmi.c | 282 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local 292 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set() 293 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set() 294 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set() 308 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set() 309 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set() 310 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set() 314 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
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A D | oaktrail_device.c | 199 p->dpll = PSB_RVDC32(MRST_DPLL_A); in oaktrail_save_display_registers() 316 PSB_WVDC32(p->dpll, MRST_DPLL_A); in oaktrail_restore_display_registers() 457 .dpll = MRST_DPLL_A, 481 .dpll = DPLL_B,
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/linux/Documentation/devicetree/bindings/clock/ti/ |
A D | dpll.txt | 18 "ti,omap3-dpll-clock", 19 "ti,omap3-dpll-core-clock", 20 "ti,omap3-dpll-per-clock", 22 "ti,omap4-dpll-clock", 23 "ti,omap4-dpll-x2-clock", 24 "ti,omap4-dpll-core-clock", 27 "ti,omap5-mpu-dpll-clock", 29 "ti,am3-dpll-j-type-clock", 31 "ti,am3-dpll-clock", 32 "ti,am3-dpll-core-clock", [all …]
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/linux/arch/arm/mach-omap1/ |
A D | sram.S | 36 strh r0, [r2] @ set dpll into bypass mode 41 strh r0, [r2] @ write new dpll value 49 lock: ldrh r4, [r2], #0 @ read back dpll value 52 tst r4, #1 << 0 @ dpll rate locked?
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/linux/Documentation/devicetree/bindings/clock/ |
A D | microchip,sparx5-dpll.yaml | 4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml# 18 const: microchip,sparx5-dpll 46 compatible = "microchip,sparx5-dpll";
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/linux/drivers/ata/ |
A D | pata_hpt3x2n.c | 317 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local 324 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer() 333 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local 335 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue() 337 flags |= dpll; in hpt3x2n_qc_issue() 340 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
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A D | pata_hpt37x.c | 982 int dpll, adjust; in hpt37x_init_one() local 985 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one() 987 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one() 1015 if (dpll == 3) in hpt37x_init_one() 1021 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
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/linux/drivers/gpu/drm/rcar-du/ |
A D | rcar_du_crtc.c | 85 struct dpll_info *dpll, in rcar_du_dpll_divider() argument 149 dpll->n = n; in rcar_du_dpll_divider() 150 dpll->m = m; in rcar_du_dpll_divider() 151 dpll->fdpll = fdpll; in rcar_du_dpll_divider() 152 dpll->output = output; in rcar_du_dpll_divider() 164 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider() 223 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local 247 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing() 250 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing() 251 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) in rcar_du_crtc_set_display_timing()
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/linux/drivers/video/fbdev/intelfb/ |
A D | intelfbhw.c | 690 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2() 693 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2() 699 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2() 1045 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local 1060 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw() 1072 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw() 1133 *dpll &= ~DPLL_P1_FORCE_DIV2; in intelfbhw_mode_to_hw() 1138 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT); in intelfbhw_mode_to_hw() 1303 dpll = &hw->dpll_b; in intelfbhw_program_mode() 1327 dpll = &hw->dpll_a; in intelfbhw_program_mode() [all …]
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/linux/arch/arm/boot/dts/ |
A D | omap54xx-clocks.dtsi | 104 compatible = "ti,omap4-dpll-m4xen-clock"; 111 compatible = "ti,omap4-dpll-x2-clock"; 177 compatible = "ti,omap4-dpll-core-clock"; 184 compatible = "ti,omap4-dpll-x2-clock"; 312 compatible = "ti,omap4-dpll-clock"; 321 compatible = "ti,omap4-dpll-x2-clock"; 357 compatible = "ti,omap5-mpu-dpll-clock"; 521 compatible = "ti,omap4-dpll-clock"; 528 compatible = "ti,omap4-dpll-x2-clock"; 588 compatible = "ti,omap4-dpll-clock"; [all …]
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A D | dra7xx-clocks.dtsi | 205 compatible = "ti,omap4-dpll-x2-clock"; 268 compatible = "ti,omap4-dpll-x2-clock"; 293 compatible = "ti,omap5-mpu-dpll-clock"; 335 compatible = "ti,omap4-dpll-clock"; 373 compatible = "ti,omap4-dpll-clock"; 411 compatible = "ti,omap4-dpll-clock"; 460 compatible = "ti,omap4-dpll-clock"; 486 compatible = "ti,omap4-dpll-clock"; 560 compatible = "ti,omap4-dpll-clock"; 1119 compatible = "ti,omap4-dpll-clock"; [all …]
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A D | am43xx-clocks.dtsi | 205 compatible = "ti,am3-dpll-core-clock"; 212 compatible = "ti,am3-dpll-x2-clock"; 251 compatible = "ti,am3-dpll-clock"; 277 compatible = "ti,am3-dpll-clock"; 295 compatible = "ti,am3-dpll-clock"; 314 compatible = "ti,am3-dpll-j-type-clock"; 558 compatible = "ti,am3-dpll-clock"; 627 compatible = "ti,am3-dpll-x2-clock";
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A D | am33xx-clocks.dtsi | 165 compatible = "ti,am3-dpll-core-clock"; 172 compatible = "ti,am3-dpll-x2-clock"; 205 compatible = "ti,am3-dpll-clock"; 221 compatible = "ti,am3-dpll-no-gate-clock"; 245 compatible = "ti,am3-dpll-no-gate-clock"; 262 compatible = "ti,am3-dpll-no-gate-j-type-clock";
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A D | omap44xx-clocks.dtsi | 134 compatible = "ti,omap4-dpll-m4xen-clock"; 141 compatible = "ti,omap4-dpll-x2-clock"; 196 compatible = "ti,omap4-dpll-core-clock"; 203 compatible = "ti,omap4-dpll-x2-clock"; 346 compatible = "ti,omap4-dpll-clock"; 355 compatible = "ti,omap4-dpll-x2-clock"; 387 compatible = "ti,omap4-dpll-clock"; 566 compatible = "ti,omap4-dpll-clock"; 582 compatible = "ti,omap4-dpll-x2-clock"; 667 compatible = "ti,omap4-dpll-j-type-clock";
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/linux/arch/arm64/boot/dts/sprd/ |
A D | sharkl3.dtsi | 123 dpll: dpll { label 124 compatible = "sprd,sc9863a-dpll";
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