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Searched refs:dpp_base (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dpp_cm.c51 struct dpp *dpp_base) in dpp2_enable_cm_block() argument
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse() argument
86 struct dpp *dpp_base, in dpp2_program_degamma_lut() argument
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl() argument
135 struct dpp *dpp_base, in dpp2_set_degamma() argument
214 struct dpp *dpp_base, in dpp2_cm_set_gamut_remap() argument
238 struct dpp *dpp_base, in dpp2_program_input_csc() argument
311 struct dpp *dpp_base, in dpp20_power_on_blnd_lut() argument
322 struct dpp *dpp_base, in dpp20_configure_blnd_lut() argument
335 struct dpp *dpp_base, in dpp20_program_blnd_pwl() argument
[all …]
A Ddcn20_dpp.c51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state() argument
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state()
76 struct dpp *dpp_base, in dpp2_power_on_obuf() argument
79 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf()
91 struct dpp *dpp_base, in dpp2_dummy_program_input_lut() argument
96 struct dpp *dpp_base, in dpp2_cnv_setup() argument
103 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup()
250 dpp2_power_on_obuf(dpp_base, true); in dpp2_cnv_setup()
255 struct dpp *dpp_base, in dpp2_cnv_set_bias_scale() argument
326 struct dpp *dpp_base, in dpp2_cnv_set_alpha_keyer() argument
[all …]
A Ddcn20_hwseq.c878 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, in dcn20_set_shaper_3dlut()
881 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); in dcn20_set_shaper_3dlut()
907 dpp_base->funcs->dpp_set_degamma(dpp_base, in dcn20_set_input_transfer_func()
917 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, in dcn20_set_input_transfer_func()
922 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, in dcn20_set_input_transfer_func()
933 dpp_base->funcs->dpp_set_degamma(dpp_base, in dcn20_set_input_transfer_func()
937 dpp_base->funcs->dpp_set_degamma(dpp_base, in dcn20_set_input_transfer_func()
941 dpp_base->funcs->dpp_set_degamma(dpp_base, in dcn20_set_input_transfer_func()
947 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); in dcn20_set_input_transfer_func()
955 dpp_base->funcs->dpp_set_degamma(dpp_base, in dcn20_set_input_transfer_func()
[all …]
A Ddcn20_dpp.h713 struct dpp *dpp_base,
717 struct dpp *dpp_base,
721 struct dpp *dpp_base,
725 struct dpp *dpp_base,
734 struct dpp *dpp_base,
738 struct dpp *dpp_base,
742 struct dpp *dpp_base,
752 struct dpp *dpp_base,
756 struct dpp *dpp_base,
765 struct dpp *dpp_base,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
A Ddcn30_dpp.c56 struct dpp *dpp_base, in dpp3_program_post_csc() argument
172 struct dpp *dpp_base, in dpp3_cnv_setup() argument
350 struct dpp *dpp_base, in dpp3_set_cursor_attributes() argument
478 struct dpp *dpp_base, in dpp3_cnv_set_bias_scale() argument
492 struct dpp *dpp_base) in dpp3_deferred_update() argument
540 struct dpp *dpp_base, in dpp3_power_on_blnd_lut() argument
560 struct dpp *dpp_base, in dpp3_power_on_hdr3dlut() argument
577 struct dpp *dpp_base, in dpp3_power_on_shaper() argument
594 struct dpp *dpp_base, in dpp3_configure_blnd_lut() argument
607 struct dpp *dpp_base, in dpp3_program_blnd_pwl() argument
[all …]
A Ddcn30_dpp_cm.c44 struct dpp *dpp_base) in dpp3_enable_cm_block() argument
51 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp3_enable_cm_block()
84 struct dpp *dpp_base, in dpp3_program_gammcor_lut() argument
133 struct dpp *dpp_base, in dpp3_power_on_gamcor_lut() argument
152 struct dpp *dpp_base, in dpp3_program_cm_dealpha() argument
163 struct dpp *dpp_base, in dpp3_program_cm_bias() argument
208 struct dpp *dpp_base, in dpp3_configure_gamcor_lut() argument
229 dpp3_enable_cm_block(dpp_base); in dpp3_program_gamcor_lut()
237 dpp3_power_on_gamcor_lut(dpp_base, true); in dpp3_program_gamcor_lut()
311 struct dpp *dpp_base, in dpp3_set_hdr_multiplier() argument
[all …]
A Ddcn30_hwseq.c84 blend_lut = &dpp_base->regamma_params; in dcn30_set_blend_lut()
87 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn30_set_blend_lut()
110 &dpp_base->shaper_params, true); in dcn30_set_mpc_shaper_3dlut()
111 shaper_lut = &dpp_base->shaper_params; in dcn30_set_mpc_shaper_3dlut()
154 if (dpp_base == NULL || plane_state == NULL) in dcn30_set_input_transfer_func()
163 dpp_base->funcs->dpp_set_pre_degam(dpp_base, tf); in dcn30_set_input_transfer_func()
170 &dpp_base->degamma_params, false)) in dcn30_set_input_transfer_func()
171 params = &dpp_base->degamma_params; in dcn30_set_input_transfer_func()
174 result = dpp_base->funcs->dpp_program_gamcor_lut(dpp_base, params); in dcn30_set_input_transfer_func()
177 if (dpp_base->funcs->dpp_program_blnd_lut) in dcn30_set_input_transfer_func()
[all …]
A Ddcn30_dpp.h585 struct dpp *dpp_base, const struct pwl_params *params);
588 struct dpp *dpp_base,
592 struct dpp *dpp_base,
596 struct dpp *dpp_base,
600 struct dpp *dpp_base,
603 void dpp3_set_pre_degam(struct dpp *dpp_base,
607 struct dpp *dpp_base,
611 struct dpp *dpp_base,
617 struct dpp *dpp_base,
621 struct dpp *dpp_base,
/linux/drivers/gpu/drm/amd/display/dc/dcn10/
A Ddcn10_dpp_cm.c161 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap() argument
240 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default() argument
310 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment() argument
351 struct dpp *dpp_base, in dpp1_cm_configure_regamma_lut() argument
365 struct dpp *dpp_base, in dpp1_cm_program_regamma_luta_settings() argument
394 struct dpp *dpp_base, in dpp1_cm_program_regamma_lutb_settings() argument
421 struct dpp *dpp_base, in dpp1_program_input_csc() argument
497 struct dpp *dpp_base, in dpp1_program_bias_and_scale() argument
518 struct dpp *dpp_base, in dpp1_program_degamma_lutb_settings() argument
547 struct dpp *dpp_base, in dpp1_program_degamma_luta_settings() argument
[all …]
A Ddcn10_dpp.c94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state() argument
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state()
196 void dpp_reset(struct dpp *dpp_base) in dpp_reset() argument
198 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_reset()
232 dpp1_cm_power_on_regamma_lut(dpp_base, true); in dpp1_cm_set_regamma_pwl()
268 struct dpp *dpp_base, in dpp1_set_degamma_format_float() argument
283 struct dpp *dpp_base, in dpp1_cnv_setup() argument
419 struct dpp *dpp_base, in dpp1_set_cursor_attributes() argument
440 struct dpp *dpp_base, in dpp1_set_cursor_position() argument
482 struct dpp *dpp_base, in dpp1_cnv_set_optional_cursor_attributes() argument
[all …]
A Ddcn10_dpp_dscl.c168 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode() argument
202 struct dpp *dpp_base, in dpp1_power_on_dscl() argument
205 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_power_on_dscl()
555 struct dpp *dpp_base, in dpp1_dscl_set_scaler_auto_scale() argument
559 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_auto_scale()
561 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_auto_scale()
715 void dpp1_dscl_set_scaler_manual_scale(struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale() argument
719 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_manual_scale()
721 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_manual_scale()
734 dpp1_power_on_dscl(dpp_base, true); in dpp1_dscl_set_scaler_manual_scale()
[all …]
A Ddcn10_dpp.h1378 struct dpp *dpp_base,
1382 struct dpp *dpp_base,
1404 struct dpp *dpp_base,
1408 struct dpp *dpp_base,
1412 struct dpp *dpp_base,
1416 struct dpp *dpp_base,
1422 struct dpp *dpp_base,
1426 struct dpp *dpp_base,
1432 struct dpp *dpp_base,
1460 struct dpp *dpp_base,
[all …]
A Ddcn10_hw_sequencer.c1707 if (dpp_base == NULL) in dcn10_set_input_transfer_func()
1717 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction); in dcn10_set_input_transfer_func()
1720 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1724 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); in dcn10_set_input_transfer_func()
1727 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); in dcn10_set_input_transfer_func()
1730 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1733 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL); in dcn10_set_input_transfer_func()
1735 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
1743 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1747 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, in dcn10_set_input_transfer_func()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Ddpp.h152 struct dpp *dpp_base,
215 struct dpp *dpp_base,
219 struct dpp *dpp_base,
226 struct dpp *dpp_base,
233 void (*dpp_full_bypass)(struct dpp *dpp_base);
236 struct dpp *dpp_base,
240 struct dpp *dpp_base,
248 struct dpp *dpp_base,
252 struct dpp *dpp_base,
256 struct dpp *dpp_base,
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_dpp.c45 struct dpp *dpp_base, in dpp201_cnv_setup() argument
52 struct dcn201_dpp *dpp = TO_DCN201_DPP(dpp_base); in dpp201_cnv_setup()
167 dpp1_program_input_csc(dpp_base, color_space, select, NULL); in dpp201_cnv_setup()
175 dpp2_power_on_obuf(dpp_base, true); in dpp201_cnv_setup()

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