Home
last modified time | relevance | path

Searched refs:dpu_hw_blk (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/
A Ddpu_rm.h27 struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
28 struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
29 struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
30 struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
31 struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
32 struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
90 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
A Ddpu_hw_blk.h11 struct dpu_hw_blk;
21 struct dpu_hw_blk { struct
A Ddpu_hw_merge3d.h28 struct dpu_hw_blk base;
44 static inline struct dpu_hw_merge_3d *to_dpu_hw_merge_3d(struct dpu_hw_blk *hw) in to_dpu_hw_merge_3d()
A Ddpu_hw_dspp.h62 struct dpu_hw_blk base;
78 static inline struct dpu_hw_dspp *to_dpu_hw_dspp(struct dpu_hw_blk *hw) in to_dpu_hw_dspp()
A Ddpu_hw_lm.h70 struct dpu_hw_blk base;
91 static inline struct dpu_hw_mixer *to_dpu_hw_mixer(struct dpu_hw_blk *hw) in to_dpu_hw_mixer()
A Ddpu_hw_intf.h81 struct dpu_hw_blk base;
98 static inline struct dpu_hw_intf *to_dpu_hw_intf(struct dpu_hw_blk *hw) in to_dpu_hw_intf()
A Ddpu_hw_pingpong.h132 struct dpu_hw_blk base;
149 static inline struct dpu_hw_pingpong *to_dpu_hw_pingpong(struct dpu_hw_blk *hw) in to_dpu_hw_pingpong()
A Ddpu_hw_ctl.h188 struct dpu_hw_blk base;
209 static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw) in to_dpu_hw_ctl()
A Ddpu_hw_top.h137 struct dpu_hw_blk base;
A Ddpu_hw_sspp.h375 struct dpu_hw_blk base;
A Ddpu_rm.c611 enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size) in dpu_rm_get_assigned_resources()
613 struct dpu_hw_blk **hw_blks; in dpu_rm_get_assigned_resources()
A Ddpu_encoder.c971 struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_mode_set()
972 struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_mode_set()
973 struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_mode_set()
974 struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL }; in dpu_encoder_virt_mode_set()
1047 struct dpu_hw_blk *hw_blk[MAX_CHANNELS_PER_ENC]; in dpu_encoder_virt_mode_set()

Completed in 21 milliseconds