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Searched refs:dsc (Results 1 – 25 of 66) sorted by relevance

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/linux/drivers/gpu/drm/amd/display/dc/dcn20/
A Ddcn20_dsc.c70 dsc->ctx->logger
88 dsc->base.ctx = ctx; in dsc2_construct()
89 dsc->base.inst = inst; in dsc2_construct()
90 dsc->base.funcs = &dcn20_dsc_funcs; in dsc2_construct()
92 dsc->dsc_regs = dsc_regs; in dsc2_construct()
93 dsc->dsc_shift = dsc_shift; in dsc2_construct()
94 dsc->dsc_mask = dsc_mask; in dsc2_construct()
96 dsc->max_image_width = 5184; in dsc2_construct()
199 dsc_config_log(dsc, dsc_cfg); in dsc2_set_config()
218 dsc_config_log(dsc, dsc_cfg); in dsc2_get_packed_pps()
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A Ddcn20_resource.h97 void dcn20_dsc_destroy(struct display_stream_compressor **dsc);
133 struct display_stream_compressor **dsc);
147 struct display_stream_compressor **dsc,
A Ddcn20_resource.c1444 struct dcn20_dsc *dsc = in dcn20_dsc_create() local
1447 if (!dsc) { in dcn20_dsc_create()
1453 return &dsc->base; in dcn20_dsc_create()
1459 *dsc = NULL; in dcn20_dsc_destroy()
1698 *dsc = NULL; in dcn20_acquire_dsc()
1702 *dsc = pool->dscs[pipe_idx]; in dcn20_acquire_dsc()
1709 *dsc = dsc_old; in dcn20_acquire_dsc()
1717 *dsc = pool->dscs[i]; in dcn20_acquire_dsc()
1730 if (pool->dscs[i] == *dsc) { in dcn20_release_dsc()
1732 *dsc = NULL; in dcn20_release_dsc()
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/linux/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c609 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
616 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
633 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
640 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
658 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
665 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
683 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
690 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
708 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
715 if (crtc_state->dsc.dsc_split) in intel_dsc_pps_configure()
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A Dintel_bios.c2021 devdata->dsc != NULL); in parse_ddi_port()
2468 kfree(devdata->dsc); in intel_bios_driver_remove()
2786 if (dsc->slices_per_line & BIT(2)) { in fill_dsc()
2787 crtc_state->dsc.slice_count = 4; in fill_dsc()
2789 crtc_state->dsc.slice_count = 2; in fill_dsc()
2792 if (!(dsc->slices_per_line & BIT(0))) in fill_dsc()
2795 crtc_state->dsc.slice_count = 1; in fill_dsc()
2799 crtc_state->dsc.slice_count != 0) in fill_dsc()
2802 crtc_state->dsc.slice_count); in fill_dsc()
2809 dsc->rc_buffer_size); in fill_dsc()
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A Dicl_dsi.c336 if (crtc_state->dsc.compression_enable) in afe_clk()
337 bpp = crtc_state->dsc.compressed_bpp; in afe_clk()
756 if (pipe_config->dsc.compression_enable) { in gen11_dsi_configure_transcoder()
896 if (crtc_state->dsc.compression_enable) { in gen11_dsi_set_transcoder_timings()
897 mul = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
920 if (crtc_state->dsc.compression_enable) in gen11_dsi_set_transcoder_timings()
921 bpp = crtc_state->dsc.compressed_bpp; in gen11_dsi_set_transcoder_timings()
1495 if (pipe_config->dsc.compressed_bpp) { in gen11_dsi_get_timings()
1618 if (crtc_state->dsc.slice_count > 1) in gen11_dsi_dsc_compute_config()
1619 crtc_state->dsc.dsc_split = true; in gen11_dsi_dsc_compute_config()
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A Dintel_dp.c863 bool dsc = false, bigjoiner = false; in intel_dp_mode_valid() local
943 if (mode_rate > max_rate && !dsc) in intel_dp_mode_valid()
1360 pipe_config->dsc.compressed_bpp = in intel_dp_dsc_compute_config()
1363 pipe_config->dsc.slice_count = in intel_dp_dsc_compute_config()
1401 pipe_config->dsc.compressed_bpp = in intel_dp_dsc_compute_config()
1417 if (pipe_config->dsc.slice_count < 2) { in intel_dp_dsc_compute_config()
1423 pipe_config->dsc.dsc_split = true; in intel_dp_dsc_compute_config()
1432 pipe_config->dsc.compressed_bpp); in intel_dp_dsc_compute_config()
1440 pipe_config->dsc.compressed_bpp, in intel_dp_dsc_compute_config()
1441 pipe_config->dsc.slice_count); in intel_dp_dsc_compute_config()
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/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
A Ddsc.h96 void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
97 …bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cf…
98 void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
100 bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
102 void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
103 void (*dsc_disable)(struct display_stream_compressor *dsc);
/linux/drivers/gpu/drm/amd/display/dc/core/
A Ddc_link_hwss.c498 dsc->ctx->logger
538 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; local
562 dsc->funcs->dsc_set_config(dsc, &dsc_cfg, &dsc_optc_cfg);
563 dsc->funcs->dsc_enable(dsc, pipe_ctx->stream_res.opp->inst);
627 pipe_ctx->stream_res.dsc->funcs->dsc_disable(pipe_ctx->stream_res.dsc);
635 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; local
640 if (!dsc)
668 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; local
690 dsc->funcs->dsc_get_packed_pps(dsc, &dsc_cfg, &dsc_packed_pps[0]);
731 struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; local
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/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_debugfs.c1323 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_clock_en_read()
1325 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_clock_en_read()
1510 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_width_read()
1512 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_slice_width_read()
1695 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_slice_height_read()
1697 dsc->funcs->dsc_read_state(dsc, &dsc_state); in dp_dsc_slice_height_read()
1876 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_bits_per_pixel_read()
2052 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_pic_width_read()
2109 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_pic_height_read()
2181 dsc = pipe_ctx->stream_res.dsc; in dp_dsc_chunk_size_read()
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/linux/drivers/net/ethernet/broadcom/
A Dsb1250-mac.c775 struct sbdmadscr *dsc; in sbdma_add_rcvbuffer() local
782 dsc = d->sbdma_addptr; in sbdma_add_rcvbuffer()
848 dsc->dscr_b = 0; in sbdma_add_rcvbuffer()
889 struct sbdmadscr *dsc; in sbdma_add_txbuffer() local
897 dsc = d->sbdma_addptr; in sbdma_add_txbuffer()
928 dsc->dscr_a = phys | in sbdma_add_txbuffer()
1058 struct sbdmadscr *dsc; in sbdma_rx_process() local
1084 dsc = d->sbdma_remptr; in sbdma_rx_process()
1085 curidx = dsc - d->sbdma_dscrtable; in sbdma_rx_process()
1087 prefetch(dsc); in sbdma_rx_process()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/
A Den_stats.h36 #define MLX5E_READ_CTR64_CPU(ptr, dsc, i) \ argument
37 (*(u64 *)((char *)ptr + dsc[i].offset))
38 #define MLX5E_READ_CTR64_BE(ptr, dsc, i) \ argument
39 be64_to_cpu(*(__be64 *)((char *)ptr + dsc[i].offset))
40 #define MLX5E_READ_CTR32_CPU(ptr, dsc, i) \ argument
41 (*(u32 *)((char *)ptr + dsc[i].offset))
42 #define MLX5E_READ_CTR32_BE(ptr, dsc, i) \ argument
43 be32_to_cpu(*(__be32 *)((char *)ptr + dsc[i].offset))
/linux/include/linux/irqchip/
A Dirq-partition-percpu.h28 struct irq_domain *partition_get_domain(struct partition_desc *dsc);
47 struct irq_domain *partition_get_domain(struct partition_desc *dsc) in partition_get_domain() argument
/linux/drivers/gpu/drm/amd/display/dc/dsc/
A Ddc_dsc.c67 const struct display_stream_compressor *dsc,
343 const struct display_stream_compressor *dsc, in dc_dsc_compute_bandwidth_range() argument
356 get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz); in dc_dsc_compute_bandwidth_range()
373 const struct display_stream_compressor *dsc, in get_dsc_enc_caps() argument
380 if (dsc) { in get_dsc_enc_caps()
381 if (!dsc->ctx->dc->debug.disable_dsc) in get_dsc_enc_caps()
382 dsc->funcs->dsc_get_enc_caps(dsc_enc_caps, pixel_clock_100Hz); in get_dsc_enc_caps()
383 if (dsc->ctx->dc->debug.native422_support) in get_dsc_enc_caps()
947 const struct display_stream_compressor *dsc, in dc_dsc_compute_config() argument
958 get_dsc_enc_caps(dsc, &dsc_enc_caps, timing->pix_clk_100hz); in dc_dsc_compute_config()
A DMakefile6 AMD_DAL_DSC = $(addprefix $(AMDDALPATH)/dc/dsc/,$(DSC))
/linux/arch/mips/mm/
A Dcerr-sb1.c466 struct dc_state *dsc = dc_states; in dc_state_str() local
467 while (dsc->val != 0xff) { in dc_state_str()
468 if (dsc->val == state) in dc_state_str()
470 dsc++; in dc_state_str()
472 return dsc->name; in dc_state_str()
/linux/drivers/gpu/drm/amd/display/dc/
A Ddc_dsc.h63 const struct display_stream_compressor *dsc,
72 const struct display_stream_compressor *dsc,
/linux/drivers/atm/
A Dzatm.h99 u32 *dsc; /* pointer to skb's descriptor */ member
102 #define ZATM_PRV_DSC(skb) (((struct zatm_skb_prv *) (skb)->cb)->dsc)
A Dzatm.c637 u32 *dsc; in do_tx() local
656 dsc[1] = 0; in do_tx()
657 dsc[2] = skb->len; in do_tx()
658 dsc[3] = virt_to_bus(skb->data); in do_tx()
668 dsc = NULL; in do_tx()
673 dsc = kmalloc(uPD98401_TXPD_SIZE * 2 + in do_tx()
675 if (!dsc) { in do_tx()
683 put = dsc+8; in do_tx()
688 dsc[1] = 0; in do_tx()
690 dsc[3] = virt_to_bus(put); in do_tx()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
A Dtls_stats.c55 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
56 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
A Dipsec_stats.c71 #define MLX5E_READ_CTR_ATOMIC64(ptr, dsc, i) \ argument
72 atomic64_read((atomic64_t *)((char *)(ptr) + (dsc)[i].offset))
/linux/drivers/gpu/drm/amd/display/dc/dml/
A DMakefile74 CFLAGS_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_ccflags)
90 CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml/dsc/rc_calc_fpu.o := $(dml_rcflags)
107 DML += dsc/rc_calc_fpu.o
/linux/drivers/irqchip/
A Dirq-partition-percpu.c235 struct irq_domain *partition_get_domain(struct partition_desc *dsc) in partition_get_domain() argument
237 if (dsc) in partition_get_domain()
238 return dsc->domain; in partition_get_domain()
/linux/tools/perf/util/
A Ddlfilter.c546 const char *dsc; in get_filter_desc() local
549 dsc = desc_fn(&long_dsc); in get_filter_desc()
550 if (dsc) in get_filter_desc()
551 *desc = strdup(dsc); in get_filter_desc()
/linux/drivers/usb/atm/
A Dueagle-atm.c1966 struct cmv_dsc_e1 *dsc = &sc->cmv_dsc.e1; in uea_dispatch_cmv_e1() local
1979 if (cmv->bFunction != dsc->function) { in uea_dispatch_cmv_e1()
1982 cmv->wIndex = cpu_to_le16(dsc->idx); in uea_dispatch_cmv_e1()
1983 put_unaligned_le32(dsc->address, in uea_dispatch_cmv_e1()
1985 cmv->wOffsetAddress = cpu_to_le16(dsc->offset); in uea_dispatch_cmv_e1()
1998 if (le16_to_cpu(cmv->wIndex) != dsc->idx || in uea_dispatch_cmv_e1()
2028 struct cmv_dsc_e4 *dsc = &sc->cmv_dsc.e4; in uea_dispatch_cmv_e4() local
2037 if (be16_to_cpu(cmv->wFunction) != dsc->function) in uea_dispatch_cmv_e4()
2048 if (be16_to_cpu(cmv->wOffset) != dsc->offset || in uea_dispatch_cmv_e4()
2049 be16_to_cpu(cmv->wGroup) != dsc->group || in uea_dispatch_cmv_e4()
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